Segmented source memory array

Static information storage and retrieval – Floating gate – Particular biasing

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36518525, G11C 1606

Patent

active

061250570

ABSTRACT:
An integrated circuit memory array has a plurality of rows of memory cells. The rows of the memory array are divided into a plurality of words. Each memory cell is in a column of the memory array, and is coupled at an output terminal to a prechargeable column output line for the column. Each memory cell of a given word is coupled at a source terminal to a local source line for the word. The local source line for each word of the memory array is selectively coupleable to ground.

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