Segmented parallel rail paths for input/output signals

Details Segmented parallel rail paths for input/output signals Segmented parallel rail paths for input/output signals

1974-12-30

1976-02-03

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

235152, 340173SP, G11C 502, G11C 506

Patent

active

039368122

ABSTRACT:
This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.

REFERENCES:
patent: 3761902 (1973-09-01), Weinberger
Cook et al. Comparison of MOSFET Logic Circuits, IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 5, 10/73.

Affiliated with

Also associated with

Rating

Segmented parallel rail paths for input/output signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Segmented parallel rail paths for input/output signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Segmented parallel rail paths for input/output signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2125367