Segmented non-volatile memory array with multiple sources with i

Details Segmented non-volatile memory array with multiple sources with i Segmented non-volatile memory array with multiple sources with i

1997-09-12

1999-09-28

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular connection

36518533, G11C 1600

Patent

active

059598840

ABSTRACT:
A flash memory array arrangement having a plurality of erase blocks which can be separately erased, preferably using negative gate erase techniques. The memory cells are arranged in each erase block to form an array of cell rows and cell columns, with the sources of the cells in each erase block connected to a common source line so as to permit separate erasure. Cells located in row have their control gates connected to a common word line and cells located in one of the columns having their drains connected to a common bit line. The cells located in each erase block have their sources connected to a common source line. Word line control circuitry functions to control the state of the word lines in read, program and erase operations. Separate erase transistors are connected to each word line for the purpose of connecting the word lines of a block to be erased to a negative voltage. The erase transistors associated with blocks other than the block being erased cause the associated word lines to be in a state so that erasure will not occur in those deselected blocks.

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