Segmented crosspoint switch array

Details Segmented crosspoint switch array Segmented crosspoint switch array

2001-01-19

2004-11-09

Horabik, Michael (Department: 2635)

Communications: electrical

Selective

Path selection

C340S002200

Reexamination Certificate

active

06816057

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to integrated circuit crosspoint switches and in particular to a crosspoint switch array composed of interconnected crosspoint switch arrays.
2. Description of Related Art
An N×M crosspoint switch, such as disclosed for example in U.S. Pat. No. 5,790,048 issued Aug. 4, 1998 to Hsieh et al, employs an array of pass transistors to selectively route input signals arriving at any of N input ports to any of M output ports.
FIG. 1
illustrates a simplified example 4×4 crosspoint switch
10
as might be implemented within a single integrated circuit. Crosspoint switch
10
includes a set of four input signal drivers D
0
-D
3
acting as input ports, a set of four receivers R
0
-R
3
acting as output ports, a switch cell array
12
for selectively providing signal paths between drivers D
0
-D
3
and receivers R
0
-R
3
, and array controller
14
. Array
12
includes four rows and four columns of switch cells
16
. Each of four conductive input lines H
0
-H
3
lines deliver the output of a separate one of drivers D
0
-D
3
to a separate row of switch cells
16
. Each of four conductive output lines V
0
-V
3
lines link a separate column of switch cells
16
to an input of a separate one of receivers R
0
-R
3
. Each switch cell
16
can selectively provide a signal path between one of input lines H
0
-H
3
and one of output lines V
0
-V
3
. Controller
14
writes single bit control data into a memory cell within each switch cell
16
, and the state of the bit controls whether or not the cell is to provide the signal path. Commands arriving on a control bus
22
from an external source such as a host computer tell controller
14
how to set the states of the control bits stored in the various switch cells
16
.
For example, when driver D
0
receives input signal IN(
0
) arriving at one of switch input terminals
18
, it buffers the signal onto its corresponding input line H
0
. Each one of the four switch cells
16
that are linked to driver input line H
0
and that are currently configured by their stored control data bit to provide a signal path, then forwards the signal to one of receivers R
0
-R
3
via its corresponding output line V
0
-V
3
. Each receiver R
0
-R
3
that receives the signal then buffers the signal onto one of four switch output terminals
20
as one of output signals OUT(
0
)-OUT(
3
).
FIG. 2
illustrates in more detail the upper left hand switch cell of the prior art crosspoint switch
10
of
FIG. 1
, including driver D
0
, input line H
0
, output line V
0
and switch cell
16
linking input line H
0
to output line V
0
and receiver R
0
. Switch cell
16
includes a pass transistor Q having its source terminal S connected to input line H
0
and its drain terminal D connected to output line V
0
. Switch cell
16
also includes a memory cell
25
for storing control data. A controller (not shown) uses control line
24
to write a bit into memory cell
25
of cell
16
. Transistor Q passes signals from input line H
0
to output line V
0
when the bit in memory cell
25
turns transistor Q on and inhibits a signal on line H
0
from passing to output line V
0
when the bit turns transistor Q off.
Although for simplicity array
12
is illustrated as a 4×4 switch cell array, switch cell arrays of similar design can be expanded to provide flexible routing paths between much larger numbers of input and output ports. Regardless of the dimensions of crosspoint switch
10
, we would like the crosspoint switch to route signals with as little delay as possible. However crosspoint switch
10
can exhibit significant signal path delay which can increase as we increase the N×M dimensions of array
12
.
Referring again to
FIG. 2
, assume that pass transistor Q of the switch cell
16
linking input line H
0
to output line V
0
is on and that the pass transistors of all other switch cells in the array are off. When input signal IN(
0
) to driver D
0
changes state, output signal OUT(
0
) produced by receiver R
0
will also change state with a time delay that is the sum of the inherent delays of driver D
0
and receiver R
0
and the signal path delay through switch cell array
12
. The signal path delay arises in large part because the output signal produced by driver D
0
on line H
0
must charge or discharge all of the shunt capacitance of the input line H
0
and output line V
0
before it can force receiver R
0
to drive OUT(
0
) to another state. That shunt capacitance includes not only the inherent capacitances of those lines and the input capacitance of receiver R
0
, it also includes the capacitance associated with all transistors connected to both input line H
0
and output line V
0
.
FIG. 3
is an impedance model of the pass transistor Q of the switch cell
16
illustrated in FIG.
2
. Input line H
0
and output line V
0
of the array are connected to the source S and drain D terminals of transistor Q respectively. The gate of transistor Q is represented by a series channel resistance RC. When transistor Q is on the series resistance is small and the switch cell provides a low impedance signal path between input line H
0
and output line V
0
. When pass transistor Q turns off, series channel resistance RC becomes large, thereby essentially breaking the signal path between input and output lines H
0
and V
0
. Regardless of the switching state of transistor Q, the driver D
0
of
FIG. 1
that buffers input signal IN(
0
) onto input line H
0
must charge the shunt capacitance CS at the transistors source terminal S. When transistor Q is on, driver D
0
must also charge the shunt capacitance CD at the drain terminal D of transistor Q.
FIG. 4
is a simple model of the capacitive loading the 4×4 array shown in
FIG. 1
places on driver D
0
when the upper left hand switch cell
16
is closed (its transistor Q being turned on to provide a signal path between the H
0
and V
0
lines) while all the other cells connected to lines H
0
and V
0
are open. When IN(
0
) is high the output stage of driver D
0
connects line H
0
through a load resistor RL
1
to a positive voltage source VCC. When IN(
0
) is low, driver D
0
grounds line H
0
through a load resistor RL
2
.
To cause the output receiver R
0
to drive the OUT(
0
) signal high or low, input driver D
0
must charge or discharge the source terminal capacitances CS of all four switch cells
16
of
FIG. 1
tied to input line H
0
, the drain terminal capacitances CD of all four switch cells
16
tied to output line V
0
, and the input capacitance of output receiver R
0
. Since charging or discharging all of that capacitance takes time, their is a delay between a change in state of the IN(
0
) signal and there is a corresponding change in state of the OUT(
0
) signal.
When we increase the size of the array, for example from 4×4 to 8×8, input and output lines H
0
and V
0
will each be connected to eight cells, rather than four. Thus driver D
0
will have to charge or discharge eight, rather than four, source capacitances and eight, rather than four, drain capacitances. Thus the signal path delay through a crosspoint switch increases with the size of the switch.
A driver charges a capacitor at a rate in inverse relation to the product of its capacitance and the series resistance between the driver's voltage source and the capacitor. Thus one way to reduce the signal path delay through array
12
is to increase the size of drivers D
0
-D
3
(i.e., reduce the size of their load resistors RL
1
and RL
2
so that they can conduct more current when charging and discharging capacitance). This reduces the time the drivers need to charge or discharge the capacitance of array
12
, thereby reducing signal path delay. However since there are practical limits to how much current a driver can supply, we need to provide other ways to further reduce signal path delay.
We could also reduce signal path delay by reducing the capacitance of pass transistors Q by making them smaller. However, smaller pass tran

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