Segmented column memory array

Details Segmented column memory array Segmented column memory array

1992-07-24

1994-05-24

LaRoche, Eugene R.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

053155416

ABSTRACT:
In an array of solid-state memory cells organized into rows and segmented columns and addressable by wordlines and bit lines, a memory cell within a segmented column is addressable by segment-select transistors which selectively connect the memory cell's pair of bit lines via conductive lines running parallel to the columns to a column decode circuit. The disposition of the segment-select transistors and the conductive lines relative to the segmented columns enables one segment-select transistor to fit in every two or more columns. In one embodiment, the segment-select transistors have double the pitch of the columns while the conductive lines have the same pitch of the columns. In another embodiment, the segment-select transistor have four times the pitch of the columns while the conductive lines have double the pitch of the columns. This enables the use of larger size segment-select transistors which are necessary for passing higher currents in devices such as EPROM or flash EEPROM. Column segmentation effectively isolates defects to individual segments and reduces the capacitance in the source and drain of an address memory cell.

REFERENCES:
patent: 5111428 (1992-05-01), Lians
patent: 5127739 (1992-07-01), Duvvury
patent: 5204835 (1993-04-01), Eitan
M. Inoue et al., "A 16 Mb DRAM With An Open Bit-Line Architecture", ISSCC Solid-State Circuits Conference, San Francisco, Feb. 1988, pp. 246-248.
M. Okada et al., "16 Mb ROM Design using Bank Select Architecture", IEEE Symposium on VLSI Circuits, Tokyo, Aug. 1988, pp. 85-86.
B. Eitan, et al., "Alternate Metal Virtual Ground (AMG)-A New Scaling Concept for Very High-Density EPROM's", IEEE Electron Device Letters, Aug. 1991, pp. 450-452.
W. Kammerer, et al., "A New Virtual Ground Array Architecture for Very High Speed, High Density EPROMS", IEEE Symposium on VLSI Circuits OISO, May 1991, pp. 83-84.

Affiliated with

Also associated with

Rating

Segmented column memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Segmented column memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Segmented column memory array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1978358