Segmented channel field effect transistors

Details Segmented channel field effect transistors Segmented channel field effect transistors

1980-10-14

1983-07-26

Davie, James W.

357 20, 357 89, H01L 2906, H01L 2978

Patent

active

043957250

ABSTRACT:
A method for the fabrication of field effect transistors with conduction channels divided into a plurality of segments, each implanted to conduct at various threshold voltages. Field effect transistors, heretofore essentially digital switching devices, may thus be fabricated for use in circuits wherein variations in applied gate voltages can result in three or more stable current levels or transistors may be designed to provide various electrical output characteristics such as that required for analog circuits, fast EPROMs, high density ROMs, etc.

REFERENCES:
patent: 4011576 (1977-03-01), Uchida et al.
patent: 4101921 (1978-07-01), Shimada et al.
patent: 4145233 (1979-03-01), Sefick et al.
patent: 4198252 (1980-04-01), Hsu
patent: 4233616 (1980-11-01), Kyomasu et al.
patent: 4242691 (1980-12-01), Kotani et al.
K. N. Ratnakamar et al., "Performance Limits of E/D NMOS VLSI", IEEE International Solid-State Circuits Conference, (1980) pp. 72-74.
T. Ito et al., "Thermal Nitride Gate FET Technology for VLSI Devices", IEEE International Solid-State Circuits Conference, (1980), pp. 74-75.

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