Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-01-29
2001-08-14
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06275051
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to apparatus for testing integrated circuits. More particularly it relates to arrangements for testing or burning-in integrated circuits at the wafer level. More particularly, it relates to a dual board tester interface having a generic tester chip board spatially separated from but electrically connected to a personalized wafer contacting board.
BACKGROUND OF THE INVENTION
The desirability of testing and burning-in integrated circuits at the wafer level is of particular interest since determination of failures at this early stage can significantly reduce costs. Wafer burn-in is an attractive technique for providing known good die for packaging in semiconductor modules including a large number of chips.
Commonly assigned U.S. Pat. No. 5,600,257, to J. Leas, et al. (the “'257 patent”), discloses an arrangement for simultaneously testing or simultaneously burning-in all the product chips on an integrated circuit wafer. The arrangement provides thermal matching between a test head and the semiconductor wafer, large scale power distribution, and electronic means to remove shorted product chips from the power distribution structure. In one embodiment the test head comprises a glass ceramic substrate, a material closely thermally matched to silicon, with test chips on one side and probes on the other side. The glass ceramic substrate has a sufficient number of thick copper power planes to provide current to each product chip on an integrated circuit wafer with a minimal voltage drop. The test chips have voltage regulators to provide a tightly controlled Vdd and ground voltage to each chip on the product wafer that is substantially independent of the current drawn by that chip and its neighbors, and substantially independent of the presence of shorted chips on the product wafer. The regulators can also be used to disconnect power to shorted chips.
Commonly assigned U.S. patent application Ser. No. 08/882,989, now U.S. Pat. No. 6,020,750, provides an improved arrangement in which a plurality of glass ceramic substrates are tiled together to provide a large area test head.
However, both of these arrangements provide tester chips in such close proximity to the product wafer that the tester chips operate at about the same temperature as the wafer during burn-in, limiting the lifetime of the tester chips. In addition, both of these arrangements for contacting all the chips on a wafer involve expensive hardware, and neither permits contact to a range of chip types that have different contact footprints.
For example, when improved technology permits a chip design to go through a “shrink,” decreasing its size and increasing the number of chips that can be fabricated on a wafer, it should not be necessary to redesign an entire test head to accommodate the increased number of chips and the new chip footprint. Thus a better solution is needed that both provides for improved tester chip lifetime and greater flexibility and lower cost for personalizing contacts, and this solution is provided by the following invention.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved test arrangement for simultaneously testing and burning-in a plurality of the product chips on an integrated circuit wafer simultaneously.
It is still another object of the present invention to provide a means of maintaining the product wafer at a burn-in temperature while maintaining tester chips at a significantly lower temperature.
It is a feature of the present invention to provide a test head having at least two boards, one thermally matched and personalized for connection to the wafer under test, the other having test chips mounted thereon there being means for connection and thermal insulation between the two carriers to provide a temperature differential there between.
It is a feature of the present invention that wafers with different chip footprints within a family of memory or logic wafers are tested with the same tester chip board but different personalized boards.
It is a feature of the present invention that a board is formed of tiled glass ceramic portions, that all individual tiles are identical, and that the individual tiles are rotated with respect to each other.
It is a feature of the present invention that thin film wiring is used on the personalized board to personalize it for connection to a product wafer.
It is a feature of the present invention that an interposer is used between the two boards to space transform wiring and provide connection there between.
These and other objects, features, and advantages of the invention are accomplished by a test head, comprising a first board and a second board. The first board has a probe side and a connection side, the probe side having probes for contacting at least one die on a product wafer, the connection side being adapted for electrical connections to the second board. The second board having a contact side and a tester chip side, the contact side has contacts for electrical connection to the connection side of the first board, the tester chip side has a tester chip for distributing power to the die or for testing the die.
REFERENCES:
patent: 4783719 (1988-11-01), Jamison et al.
patent: 5497079 (1996-03-01), Yamada et al.
patent: 5570032 (1996-10-01), Atkins et al.
patent: 5945834 (1999-08-01), Nakata et al.
patent: 5966021 (1999-10-01), Eliashberg et al.
patent: 07050325 (1995-02-01), None
patent: 07066252 (1995-03-01), None
patent: 07201935 A (1995-08-01), None
Bachelder Thomas W.
Barringer Dennis R.
Conti Dennis R.
Crafts James M.
Gardell David L.
Hogg William N.
International Business Machines - Corporation
Karlsen Ernest
Walsh Robert A.
LandOfFree
Segmented architecture for wafer test and burn-in does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Segmented architecture for wafer test and burn-in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Segmented architecture for wafer test and burn-in will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2470896