Coating apparatus – Gas or vapor deposition – Multizone chamber
Reexamination Certificate
2000-05-03
2003-08-26
Hassanzadeh, Parviz (Department: 1763)
Coating apparatus
Gas or vapor deposition
Multizone chamber
C118S695000, C118S697000, C156S345320, C204S298250, C438S687000
Reexamination Certificate
active
06610151
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains to the field of electroplating metals or alloys for filling high aspect ratio openings, such as trenches and vias, for semiconductor metallization interconnects, thin film heads, or micromachined Microelectromechanical Systems (MEMS) devices. In particular, embodiments of the present invention provide improved seed layers for electroplating copper or silver interconnects in semiconductor devices, and methods and apparatus for fabricating such improved seed layers. The improved seed layers facilitate reliable, void-free filling of small openings with high aspect ratios for so called “Damascene” and “Dual Damascene” copper and/or silver interconnects.
BACKGROUND OF THE INVENTION
As is well known in the prior art, filling trenches and/or vias formed on a wafer by electroplating copper metal to form semiconductor device interconnects (often referred to as a “Damascene” or a “Dual Damascene” process) requires that a metallization layer (often referred to in the art as a seed layer or a base layer) be formed over the wafer surface. As is also well known in the prior art, the seed layer is required: (a) to provide a low-resistance electrical path (to enables uniform electroplating over the wafer surface); (b) to adhere well to the wafer surface (usually to an oxide-containing a dielectric film such as SiO
2
, SiO
X
, or SiO
X
N
Y
); and (c) to be compatible with subsequent electroplating copper thereon.
As is. well known, the requirement of providing a low-resistance electrical path is fulfilled by choosing the seed layer to be comprised of an adequately thick, low-resistivity material.
As is further well known, since copper has a rather poor adhesion to oxide surfaces, the requirement of adhering well to the wafer surface is typically fulfilled by disposing an intermediary barrier (or adhesion) metallic layer having a strong affinity for oxygen atoms under the seed layer. As is well known in the prior art, the barrier metallic layer is formed prior to the seed layer to provide good adhesion: (a) to the oxide surface underneath it (the barrier layer provides good adhesion to the oxide surface by sharing oxygen atoms) and (b) to the seed layer above it (the barrier metallic layer provides good adhesion to the seed layer by metal to metal bonds). The barrier layer is often also referred to as an “adhesion layer” or a “liner”.In addition to providing good adhesion, the barrier layer also serves to mitigate copper out-diffusion directly into the device, or indirectly (through an insulating or a dielectric layer) into the device. As is well known in the prior art, the barrier layer. is usually chosen from the refractory metals or their alloys, such as for example, Ta, TaN
X
, Cr, CrN
X
, Ti, TiN
X
, W, WN
X
, and other alloys containing one or more of these materials.
As is still further well known, the requirement of being compatible with electroplating copper is fulfilled by choosing a seed layer that does not react spontaneously (i.e., by displacement) with copper electrolyte used during the electroplating. This is satisfied by requiring that the seed layer does not comprise a metal or alloy that is less noble than copper.
Typically, a seed layer comprises a copper layer that is deposited by a “dry” technique, such as by physical vapor deposition (“PVD”), including but not limited to sputtering, ion plating, or evaporation, or by chemical vapor deposition (“CVD”). However, the seed layer may also be deposited by a “wet” electroless plating process. In such cases, the copper seed layer thickness is typically in a range of about 300 Å to about 2,000 Å on the field (i.e., the top surface of the wafer outside trenches and via openings). In such cases, the barrier layer is typically deposited to a thickness of about 50 Å to about 500 Å (on the field) by either a PVD or a CVD technique.
The PVD techniques include, for example and without limitation, techniques such as evaporation, ion plating, and various sputtering techniques, such as DC and/or RF plasma sputtering, bias sputtering, magnetron sputtering, or Ionized Metal Plasma (IMP) sputtering. As is well known in the art, in general, due to their anisotropic and directional (“line of sight”)nature, the PVD techniques produce non-conformal deposition. For a comprehensive description of sputtering techniques and their applications, see for example an article entitled “Sputter .Deposition Processes” by R. Parsons, pp. 177-208 in
Thin Film Processes II
, edited by J. L. Vosen and W. Kern, Academic Press (1991). However, some of the PVD techniques (such as ion plating) may produce, under certain conditions, a relatively more conformal deposition. For a comprehensive description of the ion plating technique and its applications; see for example an article entitled “The Cathodic Arc Plasma Deposition of Thin Films” by P. C. Johnson, pp. 209-285 in
Thin Film Processes II
, edited by J.L. Vosen and W. Kern, Academic Press (1991). The CVD techniques include, for example and without limitation, thermal CVD, Plasma Enhanced CVD (“PECVD”), Low Pressure CVD (“LPCVD”), High Pressure CVD (“HPCVD”), and Metallo Organic CVD (“MOCVD”). For a comprehensive description of CVD techniques and their applications, see for example an article entitled “Thermal Chemical Vapor Deposition” by K. F. Jensen and W. Kern, pp. 283-368 in
Thin Film Processes II
, edited by J. L. Vosen and W. Kern, Academic Press (1991). For example, one precursor used for CVD Cu is Cupraselect™, which precursor is sold by Schumacher, Inc. Another precursor is Cu(II) hexafluoroacetylacetonate. The latter can be reacted with hydrogen gas to obtain high purity copper. As is well known in the art, in general, due to their isotropic and non-directional nature, the CVD and the electroless techniques produce conformal deposition, with substantially uniform thickness over the entire surface, including over the field and the bottom and sidewall surface&s of the openings.
Aspect ratio (“AR”)is typically defined as a ratio between a vertical dimension, D (depth), of an opening and its smallest lateral dimension, W (width, or diameter): AR=D/W. Usually, in electroplating metals or alloys to fill patterns having high aspect ratio openings (for example, in an insulator or a dielectric), the electroplating rate inside openings is slower than the rate outside openings (i.e., on the field). Further, the higher the AR of the openings, the slower the electroplating rate is inside. This results in poor or incomplete filling (voids) of high AR openings, when compared with results achieved with low AR openings. To overcome this problem in the prior art, commercial copper electrolytes contain additives that adsorb and locally inhibit (or suppress) growth outside the openings (i.e., on the field). Further, growth inhibition inside the openings is decreased from that achieved outside the openings due to slow replenishment of the additives inside the openings as compared with replenishment of the additives on the field. As a result, the deposition rate inside the openings is faster than outside, thereby facilitating void-free copper fill. Other well known reasons for voids in copper electrofill include discontinuous (or incomplete coverage of) seed layers inside the openings, and pinching-off of opening walls (for example, by overhangs of the top corners) prior to plating.
The openings may consist of vias, trenches, or patterned photoresist. As is well known, in damascene or dual damascene processes, an insulating or a dielectric layer is pattern-etched to form openings therein. Next, a barrier (or an adhesion) metallic layer and a seed layer are deposited over the insulating layer to metallize its field (the surface surrounding openings), as well as the sidewalls and bottom surfaces of the openings. Next, copper electroplating is performed over the entire metallized surface, including the top surface (the field) surrounding the openings, and inside the patterned openings. Finally, excess plated copper overlying the op
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