Multiplex communications – Wide area network – Packet switching
Patent
1988-05-20
1989-08-15
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
H24J 116
Patent
active
048582239
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a security arrangement for a telecommunications exchange system employing switching networks which handle time division multiplexed information.
Switching networks which handle time division multiplexed information "make" and "break" the communication paths in synchronism with the appearance of the multiplexed information. Typically a time division switching network suitable for handling pulse code modulated speech samples includes (i) a receive equipment including a receive sample store for the incoming path of each time division multiplex junction, (ii) a transmit equipment including a transmit sample store for the outgoing path of each time division multiplex junction and (iii) an electronic switching network providing sample information transfer paths between the various channel storage locations of the receive sample stores and the various channel storage locations of the transmit sample stores. Each sample store comprises a plurality of sample information storage locations. On the incoming or receive side of the exchange the successive channels of the received t.d.m. transmission are sequentially fed into successive storage locations of the appropriate receive sample store; whereas on the outgoing or transmit side of the exchange the channel storage locations of each transmit sample store are successively fed on to the outgoing path of the associated junction.
Such exchange systems require security arrangements and find application in the "SYSTEM X" type of telecommunications exchanges in which line concentrators and digital route switching are provided, including a peripheral card controller. Exchanges of this type are provided with two security planes. The main fault detection mechanism used for speech within the peripheral card controller is a discrepancy detector which compares the data, on a per time slot basis, from both security planes and indicates a fault when not equal. This is a good mechanism for fault detection but does not indicate which security plane is faulty. As only eight bits will be switched through the switch, no check code can be used to determine the faulty plane. In normal operation, Plane 0 data will always be chosen.
Accordingly an aim of the present invention is to provide a security arrangement in which the faulty security plane is determined by the use of path check equipment which executes a path check algorithm.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a security arrangement for a telecommunications system having two security planes, a plurality of peripheral card controllers, a plurality of peripherals; and switching arrangements interconnecting the peripheral card controllers, wherein, to determine a faulty security plane a path is provided between the controllers, and, using this path, a controller automatically performs path checks on one of the security planes, and if found to be not faulty, the controller sends data associated with that plane to the peripheral with which it is in communication.
According to an aspect of the present invention the path checks are performed by the controller transmitting path check patterns to the switching arrangement for all timeslots for which a discrepancy is detected.
According to a further aspect of the invention, the controller is arranged to monitor data received from the switching arrangement looking for the path check patterns being returned from a controller at the other end of the path which will be similarly performing a path checking operation.
BRIEF DESCRIPTION OF THE DRAWING
An embodiment of the present invention will now be described with reference to the following drawings wherein:
FIGS. 1 and 1a show a block diagram of a peripheral card controller, when FIG. 1a is placed to right of FIG. 1,
FIG. 2 shows a flow diagram of Timeslot Transitions,
FIG. 3 shows a flow diagram of Peripheral card Controller Transitions,
FIG. 4 shows a flow diagram of an Input Loop routine,
FIG. 5 shows a flow diagram of a Sync Input r
REFERENCES:
patent: 4424421 (1984-01-01), Townsend et al.
patent: 4500985 (1985-02-01), Chang
patent: 4764918 (1988-08-01), Waters
Ansell John W.
Chopping Geoffrey
Waters Richard N.
Olms Douglas W.
Scutch III Frank M.
The Plessey Company PLC
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