Secure memory having multiple security levels

Details Secure memory having multiple security levels Secure memory having multiple security levels

1997-10-03

1999-11-23

Beausoliel, Jr., Robert W.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

395186, 34082531, 34082532, 34082534, G06F 1100, G06F 704, G07D 700

Patent

active

059915196

ABSTRACT:
According to the present invention, a secured memory comprises a first level security zone having an access code controlling access to the secured memory prior to an issuer fuse being blown, a security code attempts counter preventing access to the secured memory when a predetermined number of attempts at matching the access code have been made prior to resetting the security code attempts counter, a plurality of application zones, each of the plurality of application zones comprising: a storage memory zone, an application security zone having an application zone access code controlling access to the storage memory zone after an issuer fuse has been blown, an application zone security code attempts counter preventing access to the application zone when a predetermined number of attempts at matching the application zone access code have been made prior to resetting the application zone security code attempts counter, an erase key partition having an erase key code controlling erase access to the storage memory zone after an issuer fuse has been blown, and an erase key attempts counter preventing erase access to the application zone when a predetermined number of attempts at matching the erase key code have been made prior to resetting the erase key attempts counter.

REFERENCES:
patent: 4758718 (1988-07-01), Fujisaki et al.
patent: 5508691 (1996-04-01), Castleman et al.
patent: 5606315 (1997-02-01), Gaskins
patent: 5699514 (1997-12-01), Durinovic-Johri et al.
patent: 5774546 (1998-06-01), Handelman et al.

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