Secondary ESD/EOS protection circuit

Details Secondary ESD/EOS protection circuit Secondary ESD/EOS protection circuit

1998-02-17

1999-08-31

Leja, Ronald W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 58, H02H 322

Patent

active

059461756

ABSTRACT:
To protect an input buffer from gate-oxide breakdown failure during an ESD/EOS event, an inventive secondary protection circuit is disclosed. In one embodiment, the protection circuit includes a first switch terminal connected to a pad, a second switch terminal connected to the buffer of an internal circuit, a control terminal, and an RC circuit connected between the control terminal and the supply voltage Vcc. The RC circuit delays a propagation of an ESD/EOS voltage from Vcc to the control terminal, so as to delay a generation of a conductive path between the first and second switch terminals until the ESD/EOS event lapses.

REFERENCES:
patent: 4930037 (1990-05-01), Woo
patent: 5208719 (1993-05-01), Wei
patent: 5473500 (1995-12-01), Payne et al.

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