Secondary data transfer mechanism between coprocessor and memory

Details Secondary data transfer mechanism between coprocessor and memory Secondary data transfer mechanism between coprocessor and memory

1992-11-13

1996-07-09

Shin, Christopher B.

Boots, shoes, and leggings

395847, 395280, 395154, 3642402, 3642286, 364DIG1, G06F 1300

Patent

active

055354149

ABSTRACT:
A computer system having a CPU, a memory subcircuit, a peripheral subcircuit, a primary SCSI controller, which generates a SCSI bus, a coprocessor, and a secondary SCSI controller, also attached to the SCSI bus. These components are operatively connected in such a way that the coprocessor can access the SCSI bus through the secondary SCSI controller without interfering with the CPU's ability either to run a program from the memory subcircuit or to receive data and control input from the peripheral subcircuit.

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IBM Technical Disclosure Bulletin, vol. 34, No. 6, Nov. 1991.

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