Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-12-07
2001-03-13
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S300000
Reexamination Certificate
active
06202075
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to signal processing systems, and more specifically to an adaptive filter that employs a second order error tap adaptation scheme.
BACKGROUND OF THE INVENTION
Many applications, for example, wireless systems or other communication systems, employ digital adaptive filters to reduce error caused by a communication channel. Typically, such adaptive filters include a tapped delay lines to perform a convolution operation on a series of parameters known as tap coefficients and an incoming signal. These types of adaptive filters are also known as adaptive finite impulse response (AFIR) filters. The tap coefficients typically correspond to the impulse response of a channel through which the incoming signal arrives. Thus, for time-varying channels, such adaptive (AFIR) filters need to accurately and expeditiously converge their tap coefficients to appropriate values corresponding to the varying channel characteristics.
In order to derive appropriate tap coefficients, many adaptive filters employ an algorithm known as Least Mean Square or LMS algorithm. It is evident that in time-varying applications, speed of convergence and especially, tracking of the channel becomes critical. As such, conventional LMS systems may not be sufficient to fulfill adaptive filtering requirements.
FIG. 1
illustrates a typical prior art adaptive filter that employs a Least Means Square system to calculate the tap coefficients W
k
based on the following recursive equation:
W
k
(
n
+1)=
W
k
(
n
)+&mgr;
e
(
n
)
X
k
(
nT
)
n
=0,1,
. . . L,
(1)
wherein &mgr; is known as a step-size signal and e(n) is the error signal and X is the received signal samples. As shown in
FIG. 1
, input terminal
12
is configured to receive a sequence of input signals X, which is routed through upper branch A of a tapped delay line
223
. Upper branch A includes a plurality of delay elements
42
, which are configured to provide a corresponding delayed version of signal X at their output terminal. The input terminal of each delay element is also coupled to a corresponding multiplier
40
that is configured to multiply the delayed version of signal X with a corresponding tap weight. The output terminals of each multiplier
40
is coupled to a corresponding adder
50
, so as to accumulate the numbers generated by the multipliers along branch C. The accumulated value is provided to an input terminal of a subtractor
54
, which is configured to generate an error signal e.
The other input of subtractor
54
is coupled to a reference signal
52
, which corresponds to a series of training signals that are expected to be received by the receiver. In situations wherein training signals are not available, the output signal generated by the tapped delay line is provided to a slicer circuit (not shown) and in turn to subtractor
54
. The error signal is provided to a step size multiplier
53
, which is configured to multiply the error signal by a step size &mgr;.
The output terminal of step size multiplier
53
is coupled to a plurality of tap weight generating branches
55
, which are configured to provide a tap weight signal or tap coefficient to each of the multipliers
40
.
Each tap weight generating branch comprises a multiplier
18
having one input terminal coupled to the output terminal of step size multiplier
53
. The other input terminal of each multiplier
18
is configured to receive a corresponding delayed version of signal X via the lower branch of adaptive filter
10
. As such the lower branch of adaptive filter
10
includes a plurality of delay elements
44
that are configured to provide the delayed version of signal X at the same time intervals that delay elements
42
provide delayed versions of signal X at the upper branch of adaptive filter
10
.
Each tap weight generating branch also comprises an integrator
32
that is coupled to the output terminal of the corresponding multiplier
18
. Integrator
32
typically comprises an adder
34
coupled to a delay element
36
in a closed loop arrangement. The output terminal of integrator
32
(venerates the corresponding tap weight in each branch, and is coupled to the corresponding multiplier
40
.
In an adaptive filter such as the one described in
FIG. 1
, the error signal may not converge substantially to zero while continuing to track the channel.
Thus, there is a need for an improved adaptive finite impulse response (AFIR) filter that employs a least Mean Square (LMS) algorithm where the error signal can converge substantially to zero.
SUMMARY OF THE INVENTION
The system and method of the present invention, according to one embodiment, employs an adaptive filter architecture for time-varying channels. The adaptive filter comprises a plurality of signal feedback loops coupled in parallel, each feedback loop having a correlation multiplier, a loop filter and an integrator coupled in series. Each feedback loop is configured to generate a tap signal. Each correlation multiplier is configured to generate a signal corresponding to the product of an input signal and an error signal. Each loop filter is configured to generate a signal corresponding to the sum of a signal received by the loop filter and the integral of the signal received by the loop filter. Each integrator is configured to generate a signal corresponding to the sum of a signal received by the integrator and a signal generated by the integrator during a previous time interval. The receiver is configured to sum the tap signals and to generate the error signal. The error signal corresponds to the difference between the summed tap signals and a reference signal.
In accordance with another embodiment of the invention, the signal received by the loop filter corresponds to the signal generated by the correlation multiplier, and the signal received by the integrator corresponds to the signal generated by the loop filter, while in another embodiment, the signal received by the integrator corresponds to the signal generated by the correlation multiplier, and the signal received by the loop filter corresponds to the signal generated by the integrator. Advantageously, the tap signals are linearly time-varying and the error signal converges substantially to zero. In one embodiment, wherein the input signals are received training signals, the reference signal corresponds to the transmitted training signal.
In another embodiment of the invention, the reference signal corresponds to output decision symbols generated by a slicing circuit that slices the output signals of the filter. The output signals of the slicer are referred to as “decision-directed” training signals.
REFERENCES:
patent: 5568411 (1996-10-01), Batruni
patent: 5805637 (1998-08-01), Hirosaka et al.
patent: 6009448 (1999-12-01), Jong et al.
Danfeng Xu, Yonghua Song, Gregory T. Uehara, “TP4.7: A 200MHz 9-Tap Analog Equalizer for Magnetic Disk Read Channels in 0.6m CMOS,” ISSCC Digest of Technical Papers, pp. 74-75, Feb. 1996.
Lucent Technologies - Inc.
Mai Tan V.
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