Second level cache having instruction cache parity error control

Details Second level cache having instruction cache parity error control Second level cache having instruction cache parity error control

1996-12-30

1999-02-23

Tu, Trinh L.

Excavating

371 511, 39518203, 39518506, 711 3, 711113, 711119, G06F 1100, G11C 2900

Patent

active

058752013

ABSTRACT:
Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.

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