Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-08-07
2002-05-07
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000, C341S155000, C341S118000
Reexamination Certificate
active
06384761
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to second order and higher order dynamic element matching (DEM) in multibit digital to analog data converters (DACs) and analog to digital data converters (ADCs).
2. Description of the Prior Art
Multibit DACs and ADCs have many advantages over single bit design, including better choices of noise shaping and higher possible input signal range. The most significant drawback of multibit converters is the required matching between elements in order to achieve linearity and low noise.
High performance DACs and ADCs are useful in many applications, for example for the processing of audio signal, with the signal processing functions being performed in the digital domain, and for network modems, where high bandwidth and low noise are important. The preferred DACs and ADCs for these applications are based upon delta sigma modulators. Delta sigma modulation incorporates a noise-shaping technique whereby the noise of a quantizer operating at a frequency much greater than the bandwidth is moved to frequencies not of interest in the output signal. A filter after the quantizer removes the out of band noise. The resulting system synthesizes a high resolution data converter, but is constructed from low resolution building blocks. A good overview of the theory of delta sigma modulation is given in “Delta-Sigma Data Converters,” by Norsworthy, Schreier and Temes, IEEE Press, 1997. Another useful reference is “A 2.5MSample/s Multi-bit DS CMOS ADC with 95 dB SNR” by Geerts et al, ISSCC 2000/Paper WA 20.2, Feb. 9, 2000.
FIG. 1
shows a conventional multibit delta sigma DAC. A delta sigma DAC generally comprises a multibit noise shaping delta sigma modulator
104
having input signal
102
and feeding a thermometer type decoder
106
. The output of decoder
106
is the input to parallel unit element DAC
108
. The output of parallel unit element DAC
108
is analog signal
114
. DAC
108
operates at the clock level of delta sigma modulator
104
.
In a delta sigma converter, there are three major factors which contribute to dynamic range, the order of the loop (generally the number of cascaded integrators in the loop filter), the number of levels of the quantizer, and the over sample ratio. In practice, delta sigma modulators are generally at least second order, because higher order modulators better reduce noise in the signal band, due to improved prediction of the in band quantization error. Thus, the resulting signal to noise ratio is better. U.S. Pat. No. 5,461,381 provides a good reference on implementation details of switched capacitor sigma delta converters.
An M+1 level parallel unit element DAC
108
can be built using M elements
110
since the possible digital output levels range from 0 elements being active up to M elements being active. The Kth output level is generated by activating K approximately equal-valued elements
110
(typically resistors, transistor current sources or capacitors) and summing the charges or currents in summer
112
to generate the analog output signal
114
. Parallel unit element DAC
108
produces relatively few output levels, but the levels must be extremely accurate.
Element mismatch can be converted into an out of band noise signal (later filtered out) using dynamic element matching (DEM). One DEM technique, called dynamic element rotation, is shown in
FIG. 2
(Prior Art). Dynamic element rotation modulates the nonlinearity error around the subharmonics of the sampling clock frequency by making the mismatch noise a periodic signal. Rather than driving DAC
108
directly, decoder
202
feeds a barrel shifter
204
, which rotates the connections between thermometer decoder
202
and DAC
108
each clock pulse (per counter
206
). The counter in incremented by the number of elements used in each cycle. This guarantees that all elements are used equally over the long term, which shapes the mismatch noise in a first order way. The drawback of this system is that the remaining noise tends to be tonal for certain inputs, which is generally undesirable.
FIG. 3
(Prior Art) shows another possible DEM technique. M noise shaping elements
301
each have nominal transfer function of H
2
. Vector quantizer
310
sorts the M sy inputs, and assigns a 1 to the v greatest elements, where v is the current output of multibit delta sigma converter
104
. The noise shaping loop of elements
301
comprises filter
311
and adders
312
and
313
. Minimize block
320
keeps all of the noise shaping loops
301
in a bounded range. For second order noise shaping, H
2
is chosen as (1−z
−1
)
2
. Thus, the transfer function of block
311
is −2z
−1
+z
−2
. The assumption that the added noise is white is a very poor one, and the performance of such a system is limited. Vector quantizer
310
is forced to make “bad” decisions, as there is only one way (for example) to pick 4 out of 4 elements. In addition, it is easy for overload of the state variables of filter
311
to occur, especially with a high input signal. When this happens, the noise shaping is lost. For more detail, refer to “Delta-Sigma Data Converters,” by Norsworthy, Schreier and Temes, IEEE Press, 1997, chapter 8.
FIG. 4
(Prior Art) is a block diagram which shows a delta sigma digital to analog converter equivalent to that shown in FIG.
3
. Each second order noise shaper
401
includes a clipper
406
. Like the noise shaper of
FIG. 3
(prior art), noise shaper
401
has a block transfer function of 1−2z
−1
+z
−2
. When clipping does not occur, this system performs as a second order noise shaper. In this implementation, vector quantizer
410
finds the smallest v elements of sy (where v is the current output of delta sigma modulator
106
), as the output of
410
is assumed to be positive for selected elements.
Note that the first integral of the past error is lost in the
FIG. 4
system when clipping happens. In simulation, it is found that overflow is relatively common, especially for high level inputs. When overflow does take place, the performance degrades dramatically.
A need remains in the art for improved second and higher order dynamic element matching for multibit data converters.
SUMMARY OF THE INVENTION
An object of the present invention is to provide improved second and higher order dynamic element matching for multibit data converters.
In a multibit data converter having an output parallel unit element converter fed by a multibit signal, noise shaping dynamic element matching apparatus for selectively activating units in the converter comprises a plurality of noise shaping components, each having as an input one signal to the converter, including a first integrator having as its input the input to the component, a second integrator having as its input the output of the first integrator, and a summer for adding the output of the first integrator and the output of the second integrator to form a component output, wherein a signal in the second integrator is clipped; and a vector quantizer for ordering the component outputs and activating converter elements according to the ordering.
The gain of the second integrator preferably is greater than zero and less than the gain of the first integrator. For efficiency, a selected signal to the parallel unit element converter can be provided as a component input, and this selected signal subtracted from the component inputs.
In another embodiment of a multibit data converter having an output parallel unit element converter fed by a multibit signal, the noise shaping dynamic element matching apparatus for selectively activating units in the converter comprises a plurality of noise shaping components, each having as an input one signal to the converter, each component including a first integrator having as its input the input to the component and providing a first output of the component, and a second integrator having as its input the output of the first integrator and providing a second output of the component, and a vect
Bales Esq. Jennifer L.
Cirrus Logic Inc.
Mai Lam T.
Shifrin Esq. Dan A.
Tokar Michael
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