Searchline control circuit and power reduction method

Details Searchline control circuit and power reduction method Searchline control circuit and power reduction method

2003-02-04

2004-06-01

Phung, Anh (Department: 2824)

Static information storage and retrieval

Powering

Conservation of power

C365S154000

Reexamination Certificate

active

06744688

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM). In particular, the present invention relates to a circuit and method for reducing power consumption of search lines and match lines in a CAM device.
BACKGROUND OF THE INVENTION
In many conventional memory systems, such as random access memory, binary digits (bits) are stored in memory cells, and are accessed by a processor that specifies a linear address that is associated with the given cell. This system provides rapid access to any portion of the memory system within certain limitations. To facilitate processor control, each operation that accesses memory must declare, as a part of the instruction, the address of the memory cell/cells required. Standard memory systems are not well designed for a content based search. Content based searches in standard memory require software based algorithmic search under the control of the microprocessor. Many memory operations are required to perform a search. These searches are neither quick nor efficient in using processor resources.
To overcome these inadequacies an associative memory system called Content Addressable Memory (CAM) has been developed. CAM allows cells to be referenced by their contents, so it has first found use in lookup table implementations such as cache memory subsystems and is now rapidly finding use in networking systems. CAM's most valuable feature is its ability to perform a search and compare of multiple locations as a single operation, in which search data is compared with data stored within the CAM. Typically search data is loaded onto search lines and compared with stored words in the CAM. During a search-and-compare operation, a match or mismatch signal associated with each stored word is generated on a matchline, indicating whether the search word matches a stored word or not. A typical CAM block diagram is shown in FIG.
1
. The CAM
10
includes a matrix, or array
100
, of CAM cells (not shown) arranged in rows and columns. For a ternary CAM, the cells are typically either DRAM or SRAM type, and store one of three states: logic “1”, logic “0” and “don't care”, as two bits of data. A predetermined number of CAM cells in a row store a word of data. An address decoder
12
is used to select any row within the CAM array
100
to allow data to be written, via write data register
17
, into or read out of the selected row. Although most commonly, data is written or loaded into the CAM and searched. Data access circuitry such as bitlines and column selection devices, are located within the array
100
to transfer data into and out of the array
100
. The comparand, mask registers
15
, search data register
500
and write data registers
17
receive data from the data I/O block
20
. Located within CAM array
100
for each row of CAM cells are matchline sense circuits (not shown). The matchline sense circuits are used during search-and-compare operations for outputting a result indicating a successful or unsuccessful match of a search word against the stored word in the row. The results for all rows are processed by the priority encoder
400
to output the address (Match Address) corresponding to the location of a matched word. The match address is stored in match address registers
300
before being output by the match address output block
26
. Since it is possible that more than one row will match the search word, the priority encoder
400
generates the highest priority address corresponding to a matched word. Search data register
500
is responsible for asserting search word data onto the searchlines within the array
100
. Each search data register
500
receives its respective data signals (not shown), for driving one bit of the search word data onto a pair of complementary searchlines. Additional components of the CAM include the control circuit block
14
, the flag logic block
16
, the voltage supply generation block
18
, various control and address registers
22
and a refresh counter
28
.
CAM cells are generally either SRAM based cells or DRAM based cells. Until recently, SRAM based CAM cells have been most common because of their speed and compatibility with standard logic processes. However, to provide ternary CAMs, i.e. CAMs having cells which store one of three possible states: a “0”, “1” or “don't care”, ternary SRAM based cells typically require many more transistors compared to a typical DRAM based cell of six transistors. As a result, ternary SRAM based CAMs have a much lower packing density than ternary DRAM cells.
FIG. 2
shows a typical ternary DRAM type CAM cell
101
as described in Canadian Patent Application No. 2,266,062, filed Mar. 31, 1999, the contents of which are incorporated herein by reference. Cell
101
has a comparison circuit which includes an n-channel search transistor
102
connected in series with an n-channel compare transistor
104
between a matchline ML and a tail line TL. A search line SL is connected to the gate of search transistor
102
. The storage circuit includes an n-channel access transistor
106
having a gate connected to a wordline WL and connected in series with capacitor
108
between bitline BL and a cell plate voltage potential VCP. Charge storage node CELL
1
is connected to the gate of compare transistor
104
to turn on transistor
104
if there is charge stored on capacitor
108
i.e. if CELL
1
is logic “1”. The remaining transistors and capacitor replicate transistors
102
,
104
,
106
and capacitor
108
for the other half of the ternary data bit, and are connected to corresponding lines SL* and BL* and are provided to support ternary data storage. Together they can store a ternary value representing logic “1”, logic “0”, or “don't care”.
Ternary Value
CELL1
CELL2
0
0
1
1
1
0
“Don't Care”
0
0
Lines SL, SL*, BL and BL* are common to all cells of the column, and lines ML, TL and WL are common to all cells of a word in the row. The tail line TL is typically connected to ground and all the transistors are n-channel transistors. The description of the operation of the ternary DRAM cell is detailed in the aforementioned reference.
FIG. 3
shows a typical SRAM cell of the prior art used to implement the ternary CAM cell. The SRAM type CAM cell of
FIG. 3
includes a CMOS cross-coupled latch connected to a pair of bitlines via access transistors. The cross-coupled latch consists of p-channel transistors
110
and
111
, and n-channel transistors
112
and
113
, where p-channel transistor
110
and n-channel transistor
112
, and p-channel transistor
111
and n-channel transistor
113
, form respective complimentary pairs connected in series between the VDD voltage supply and ground. N-channel access transistor
114
couples bitline BL to the shared source-drain of transistors
110
and
112
, and n-channel access transistor
115
couples bitline BL* to the shared source-drain of transistors
111
and
113
. The gates of access transistors
114
and
115
are connected to a common wordline WL for the row. A single output line
116
connects the shared source-drain of transistors
111
and
113
to the comparison circuit of FIG.
4
. Since the CAM cell of
FIG. 3
only stores one bit of information, a second identical circuit would be required to store a second bit of information in order to provide ternary data storage. It will be apparent to one skilled in the art that a ternary SRAM type CAM cell is implemented with many more transistors than the previously discussed ternary DRAM type CAM cell shown in FIG.
2
.
FIG. 4
shows a ternary comparison circuit of the prior art used with the ternary SRAM type CAM cell previously discussed in FIG.
3
. The circuit compares stored CAM cell data against searchline data, and discharges a precharged matchline to indicate the mis-match condition. Otherwise, the precharged matchline remains at the precharge voltage to indicate the match condition. The ternary comparison circuit of
FIG. 4
consists of n-channel compare transistors
120
and
122
connected in series between searchlines SL an

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