Sealed semiconductor chip and process for fabricating sealed sem

Details Sealed semiconductor chip and process for fabricating sealed sem Sealed semiconductor chip and process for fabricating sealed sem

1996-10-17

1999-01-05

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257641, 257786, 257760, 257640, H01L 2180, H01L 2934

Patent

active

058567054

ABSTRACT:
Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

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T.C. Hall, et al., "Photonitride Passivating Coating For IC's", NASA Tech Briefs, vol. 5, No. 2, Summer 1980, pp. 231-232.

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