Sealed nitride layer for integrated circuits

Details Sealed nitride layer for integrated circuits Sealed nitride layer for integrated circuits

2006-05-18

2009-10-20

Pham, Hoai v (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

C257S575000, C257SE27053

Reexamination Certificate

active

07605445

ABSTRACT:
The present invention relates to an integrated circuit. The integrated circuit includes a substrate, at least one device region formed in the substrate, a patterned layer of oxide, a first and second layer of nitride and at least one metal contact region. The patterned layer of oxide is formed over a surface of the substrate, wherein the patterned layer provides at least one opening to the surface of the substrate adjacent the at least one device region. The first layer of nitride is formed over the patterned oxide layer. The second nitride layer is formed along sidewalls to the at least one opening. The patterned oxide layer is sealed with the first and second nitride layers. The at least one metal contact region is formed in the at least one opening.

REFERENCES:
patent: 5679601 (1997-10-01), Wu
patent: 6486033 (2002-11-01), Tu et al.
patent: 6573548 (2003-06-01), Leung et al.
patent: 2001/0012655 (2001-08-01), Nordstom et al.
S. Wollf and R. N. Tauber, “Silicon Processing for the VLSI Era: vol. 1—Process Technology,” 1986, pp. 321-324, Publisher: Lattice Press, Sunset Beach, CA, Published in: US.

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