Sealed cavity arrangement method

Details Sealed cavity arrangement method Sealed cavity arrangement method

1996-01-30

1997-01-07

Quach, T. N.

Fishing, trapping, and vermin destroying

437 7, 437901, 148DIG12, H01L 2177, H01L 2178

Patent

active

055916791

ABSTRACT:
This invention relates to a method for making sealed cavities on silicon wafer surfaces by anodic bonding and with electrically insulated conductors through the sealing areas to connect functional devices inside the cavities to electrical terminals outside said cavities. Said conductors are provided by the use of doped buried crossings in a single crystal silicon substrate, thereby also allowing different kinds of integrated silicon devices, e.g. sensors to be made. Further, the invention relates to a device made by the novel method.

REFERENCES:
patent: 4023562 (1977-05-01), Hynecek et al.
patent: 4291293 (1981-09-01), Yamada et al.
patent: 4295115 (1981-10-01), Takahashi et al.
patent: 4670969 (1987-06-01), Yamada et al.
patent: 4802952 (1989-02-01), Kobori et al.
patent: 4975390 (1990-12-01), Fujii et al.

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