Seal ring for reducing noise coupling within a...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With contact or metallization configuration to reduce...

Reexamination Certificate

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Details

C257S499000, C257S491000, C257S484000, C257S483000, C257S170000, C257SE23114, C257SE29007

Reexamination Certificate

active

07898056

ABSTRACT:
Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.

REFERENCES:
patent: 6492716 (2002-12-01), Bothra et al.
patent: 2005/0110119 (2005-05-01), Chen
patent: 2006/0197214 (2006-09-01), Chen
patent: 2007/0001004 (2007-01-01), Mallikarjunaswamy et al.
patent: 2008/0061397 (2008-03-01), Uchida
patent: 2009/0250783 (2009-10-01), Nakashiba
patent: 2009/0294929 (2009-12-01), Lee et al.
patent: 2010/0102421 (2010-04-01), Chang et al.

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