Seal ring for integrated circuits

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation

Reexamination Certificate

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Details

C257S373000, C257S409000, C257S490000, C257S494000, C257S495000, C257S544000

Reexamination Certificate

active

06879023

ABSTRACT:
The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically isolated from the remainder of the substrate, such as a well region of a conductivity type opposite that of the substrate, extends around the major portion of the periphery of the substrate. A gap is left between the two ends of the elongate region along the minor portion of the periphery of the substrate not covered by the elongate region. A conductive seal ring is formed around the periphery of the substrate at the elongate region and spans the gap between the ends of the elongate region. The substrate of the semiconductor die is only brought into electrical contact with the seal ring at the gap between the ends of the elongate region.

REFERENCES:
patent: 4280070 (1981-07-01), Reese et al.
patent: 4988636 (1991-01-01), Masleid et al.
patent: 5072287 (1991-12-01), Nakagawa et al.
patent: 5475255 (1995-12-01), Joardar et al.
patent: 5491358 (1996-02-01), Miyata
patent: 5652459 (1997-07-01), Chen
patent: 5814889 (1998-09-01), Gaul
patent: 6028347 (2000-02-01), Sauber et al.
patent: 6424022 (2002-07-01), Wu et al.
patent: 55-21110 (1980-02-01), None

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