Seal ring and die corner stress relief pattern design to...

Details Seal ring and die corner stress relief pattern design to... Seal ring and die corner stress relief pattern design to...

2005-04-05

2005-04-05

Niebling, John F. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Groove

C257S623000, C257S626000, C257S632000, C257S698000, C257S728000, C333S246000, C333S260000

Reexamination Certificate

active

06876062

ABSTRACT:
An apparatus and method for protecting die corners in a semiconductor integrated circuit. At least one irregular seal ring having two sides can be configured, wherein the irregular seal ring is located at a corner of a die utilized in fabricating a semiconductor integrated circuit. A dummy configuration for stress relief can then be arranged, wherein the dummy configuration is located at the two sides of the at least one irregular seal ring, thereby protecting the corner of the die against thermal stress and the semiconductor integrated circuit against moisture and metallic impurities. The irregular seal ring can be configured to generally comprise a non-rectangular seal ring. The irregular seal preferably comprises an octangular seal ring.

REFERENCES:
patent: 6028347 (2000-02-01), Sauber et al.
patent: 6028497 (2000-02-01), Allen et al.
patent: 20020157082 (2002-10-01), Shau

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