Sea-of-cells array of transistors

Details Sea-of-cells array of transistors Sea-of-cells array of transistors

2000-11-01

2002-12-03

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S758000

Reexamination Certificate

active

06489641

ABSTRACT:

The invention concerns an Integrated Circuit (IC) architeure in which individual transistors, each of which resides in a “cell,” are arranged in a matrix-like array, thereby forming a “sea” of the cells.
Groups of the cells are interconnected among themselves, by local interconnect, into functional units. (Some of these units are called “MACROs.”) The local interconnect in the units is prohibited from occupying certain layers, such as second-layer metal. The prohibited layer is used instead to connect the individual units to each other.
BACKGROUND OF THE INVENTION
Several practices, common in the prior art, tend to utilize resources in integrated circuits (ICs) in an inefficient manner. These are:
1. The use of metal level
2
for local interconnect.
2. The use of metallization located above a row of transistors for interconnect for other transistors, rendering the row of transistors non-usable.
3. The use of a cell spacing (or “row pitch”) in a MACRO which is different from that of the rest of the array of standard cells into which the MACRO is embedded.
These practices will be addressed individually.
Metal Level
2
is Used for Local Interconnect
CMOS Inverters Generally
FIG. 1
illustrates a common approach to constructing a CMOS inverter. A p-well and an n-well are constructed in a silicon substrate
3
. A gate G, commonly made of polysilicon, extends across the wells.
In the p-well, an electric field produced by the gate G generates an n-type channel (not shown) in which electrons flow from a source S to a drain D. In the n-well, this electric field generates an opposite type of channel, namely, a p-type channel (not shown), in which holes flow from a source S to a drain D. This electric field modulates the flow of the electrons and holes, and thus modulates the current flowing through the inverter.
Electric power for the inverter is provided by bus lines Vss and Vdd. These bus lines are generally fabricated in first-layer metal, or METAL
1
in FIG.
2
. (“POLY” in that Figure refers to polysilicon.)
Trace T is Generally Located in METAL
2
The two drains D in
FIG. 1
are connected by an interconnect trace T. The Inventor herein has observed that this trace T is fabricated using second-layer metal, which is labeled METAL
2
in FIG.
2
. Locating this trace T in METAL
2
presents obstacles to routing other traces, as
FIG. 3
illustrates. For example, trace TT cannot take the path shown, because trace T blocks the way. Thus, the freedom of routing of traces such as T is limited by the local interconnect traces T.
(
FIG. 1
has been simplified for ease of illustration. Insulating layers are not shown, and the vias V have been simplified.
FIG. 4
illustrates a more detailed view. Vias are not pure vertical columns, as in the simplified
FIG. 1
, but, for various technical reasons, take the form shown in
FIG. 5.
)
When Macros are Embedded, the Power Busses Become Disrupted
Standard Cell Arrays Generally
The cells of a standard cell array typically contain a simple logic function, such as an inverter, a NAND gate, or a D-flip flop. The transistors in these cells are specifically designed for the drive requirements of the particular cell, and spacing of these transistors depends upon such factors as the location of contacts within the cells.
The spacing, or pitch, between rows of cells is determined by (a) the number of interconnect lines fabricated from METAL
1
(shown in
FIG. 2
) and (b) the cell height. The cell height, in turn, depends upon the transistor configuration within the cells.
FIG. 6
illustrates these terms.
The interconnect lines fabricated from METAL
1
are typically laid out by an automated device, or computer program, called a “router,” or “auto-router.” Different routers have different algorithms for laying out the lines, so that different routers will produce different interconnect patterns, even though the end result of the connections may be the same.
Thus, in general, the row pitch is determined by (a) the router used to interconnect the cells in the standard cell array and (b) the height of the individual cells.
Wiring is Primary Consumer of Space
It is very important to efficiently arrange the wiring in an IC because, in general, the wiring running from transistor-to-transistor consumes more space than the transistors themselves. (The wiring consists of traces fabricated from the METAL layers shown in
FIG. 2.
) Restated, the size of the IC is generally determined by how efficiently the wiring can be routed and compacted, and not by how many transistors the IC contains.
In a standard cell array, such as that shown in
FIG. 6
, when more wiring is needed, it is common to use the METAL, shown in
FIG. 2
, which is located between rows of cells in
FIG. 6
, such as at location L
1
. If additional METAL
2
is required, the cells are then spaced apart, as shown in
FIG. 6
, so that metal lines can be run between them, as indicated.
Embedding MACROs into Standard Cell Arrays Wastes Space
MACROs are frequently incorporated into ICs containing standard cell arrays. A MACRO is a block of transistors which have been optimized to perform a specific function. In a MACRO, the layout of the individual transistors, their operating characteristics, and their interconnections may have all been matched to each other for optimum performance. Thus, typically, a MACRO is constructed from different sizes of transistors, which are embedded into the standard cell array as shown in FIG.
7
.
Since, in general, the ROW PITCH of the MACRO is different from that of the standard cell array, the power busses Vdd and Vss will be interrupted. To accommodate this interruption, the power busses are re-designed as a ring which surrounds the MACRO.
FIG. 7
shows such a ring generically.
Recapitulation
Therefore,
1. The use of METAL
2
for local interconnect presents obstacles to the free routing of other interconnects over the cell, as illustrated in FIG.
3
.
2. In a standard cell array, the ROW PITCH is determined by the cell height and the number of lines of METAL
1
interconnect placed between the cell rows by the auto-router.
3. The row pitch in a MACRO is generally different from that of a standard cell array into which the MACRO is embedded. This different row pitch disrupts the power bus system, requiring a ring of power busses to be formed around the MACRO. This approach wastes space within the IC.
OBJECTS OF THE INVENTION
It is an object of the invention to provide an improved approach to the layout of an integrated circuit.
It is a further object to provide a method of compacting interconnections in integrated circuits.
It is yet a further object of the invention to provide a method for improving the performance of the integrated circuit after the layout has been completed, without requiring a new layout to be generated.
SUMMARY OF THE INVENTION
In one form of the invention, a MACRO, when embedded within a standard cell array, uses the same row pitch as that of the standard cell array itself.
In another form of the invention, the interconnect within the standard cell is confined to METAL
1
and polysilicon layers, so that METAL
2
is free for routing over the cell.
In still another form of the invention, the diffusion layer of the transistors within the standard cells is designed for optimum performance after the layout has been completed, rather than at another time.


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