Scribe seal structure and method of manufacture

Semiconductor device manufacturing: process – Semiconductor substrate dicing

Reexamination Certificate

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C438S465000, C438S114000

Reexamination Certificate

active

06709954

ABSTRACT:

FIELD OF THE INVENTION
This invention relates, in general, to semiconductor components and, more particularly, to scribe seal structures on semiconductor components.
BACKGROUND OF THE INVENTION
Typically, a plurality of semiconductor components are manufactured from a single semiconductor wafer. The semiconductor wafer is partitioned into a plurality of rectangular regions called die or chips, where adjacent chips are separated by scribe lines. The manufacturing process is designed so all the chips on a single semiconductor wafer are identical. Once the transistor circuitry and associated metal interconnects have been fabricated in the chip active region, the semiconductor wafers are sawed along the scribe lines to separate or singulate the semiconductor wafer into a plurality of semiconductor chips. The chips are then packaged, tested, and shipped to customers.
Sawing or cutting the semiconductor wafer stresses it and causes microcracking to occur. The microcracks can migrate to the active regions of the chips and damage the circuitry fabricated in the semiconductor wafer. To prevent or arrest microcrack migration, designers place scribe seal structures between the active region of the chip and the scribe lines. These structures prevent microcracks formed during sawing along the scribe lines from migrating to the active region, thereby preventing the microcracks from damaging the semiconductor components.
FIG. 1
illustrates an enlarged cross-sectional view of a scribe seal structure
100
in accordance with the prior art. Scribe seal structure
100
comprises a semiconductor substrate
102
having a dielectric layer
104
disposed thereon. Dielectric layer
104
has an opening
106
filled with copper that forms a copper layer
108
. A capping layer
110
is disposed on dielectric layer
104
and copper layer
108
. A dielectric layer
112
having a plurality of openings
114
is disposed on capping layer
110
. Openings
114
extend through capping layer
110
and expose portions of copper layer
108
. Openings
114
are filled with copper to form copper-filled vias
115
. A dielectric layer
116
having an opening
118
is formed on dielectric layer
112
and copper-filled vias
115
. Opening
118
is filled with copper that forms a copper layer
120
. A capping layer
124
is disposed on dielectric layer
116
and copper layer
120
. A dielectric layer
126
having a plurality of openings
128
is disposed on capping layer
124
. Openings
128
extend through capping layer
124
and expose portions of copper layer
120
. Openings
128
are filled with copper to form copper-filled vias
129
. A dielectric layer
132
having an opening
134
is formed on dielectric layer
126
and copper-filled vias
129
. Opening
134
is filled with copper that forms a copper layer
135
. A capping layer
136
is disposed on dielectric layer
132
and copper layer
135
. A dielectric layer
137
having a plurality of openings
138
is disposed on capping layer
136
. Openings
138
extend through capping layer
136
and expose portions of copper layer
135
. Openings
138
are filled with copper to form copper-filled vias
139
. A dielectric layer
140
having an opening
141
is formed on dielectric layer
137
and copper-filled vias
139
. Opening
141
is filled with copper that forms a copper layer
142
. A capping layer
144
is disposed on dielectric layer
140
and copper layer
142
. A drawback of scribe seal structure
100
is that openings
114
,
128
, and
138
are formed using Reactive Ion Etching (RIE) that terminates on copper. Because these openings terminate on copper, the RIE causes sputtering of the copper from copper layers
108
,
120
, and
135
, that are exposed by openings
114
,
128
, and
138
, respectively. As those skilled in the art are aware, copper is a silicon contaminant. Thus, the sputtered copper contaminates the silicon substrate which leads to device failure.
Accordingly, what is needed is method and structure for forming scribe seals that does not cause copper to be sputtered.
SUMMARY OF THE INVENTION
The present invention satisfies the foregoing need by providing a scribe seal, a method for fabricating the scribe seal, and a semiconductor component including the scribe seal. In accordance with one aspect of the present invention, the scribe seal comprises a semiconductor substrate having a crack arrest structure disposed on a first portion of a major surface. A dielectric layer is disposed on a second portion of the major surface, where the dielectric layer is adjacent the crack arrest structure. Another crack arrest structure is disposed on the dielectric layer that is disposed on the major surface. This crack arrest structure is laterally spaced apart from the crack arrest structure disposed on the major surface. The crack arrest structures cooperate to form a scribe seal.
In accordance with another aspect, the present invention includes a method for manufacturing a scribe seal. A semiconductor substrate having a major surface is provided. A layer of dielectric material is disposed on a portion of the major surface and an opening is formed in the layer of dielectric material to expose a portion of the major surface. The opening is filled with a crack arresting material to form a crack arrest structure. A layer of dielectric material is formed on the crack arresting material and the layer of dielectric material disposed on the major surface. An opening is formed in the second layer of dielectric material, which opening exposes a portion of the first layer of dielectric material. The opening in the second layer of dielectric material is filled with crack arresting material to form a crack arrest structure. The crack arrest structures cooperated to form a scribe seal.
In accordance with yet another aspect, the present invention includes a semiconductor component having a scribe seal in accordance with an embodiment of the present invention.


REFERENCES:
patent: 5933758 (1999-08-01), Jain
patent: 6022791 (2000-02-01), Cook et al.
patent: 6078068 (2000-06-01), Tamura
patent: 6268289 (2001-07-01), Chowdhury et al.
patent: 6300223 (2001-10-01), Chang et al.
patent: 6326301 (2001-12-01), Venkatesan et al.
patent: 6365958 (2002-04-01), Ibnabdeljalil et al.
patent: 6412786 (2002-07-01), Pan

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