Screenable power chip mosaics, a method for fabricating large po

Details Screenable power chip mosaics, a method for fabricating large po Screenable power chip mosaics, a method for fabricating large po

1988-05-02

1989-05-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 51, 357 45, 364491, H01L 2170

Patent

active

048290149

ABSTRACT:
An additive process allowing discretionary interconnection of only the acceptable devices on a semiconductor wafer includes screen printing a polyimide layer over the wafer to form vias over all of the device contact pads on the wafer while coating the remainder of the wafer. The devices are then individually tested through the vias and, when a device is determined to be unacceptable according to predetermined specifications, the vias above that device are filled with polyimide. A layer of metal is next deposited over the entire wafer by evaporation and makes electrical contact with only the acceptable devices since the unacceptable devices have been blocked off. The metal layer is thereafter patterned to leave an interconnection pattern wherein only the acceptable devices on the wafer are electrically connected.

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