Scrambled video signal processor

Details Scrambled video signal processor Scrambled video signal processor

1986-09-29

1988-02-16

Groody, James J.

Facsimile and static presentation processing

Static presentation processing

Attribute control

380 10, 380 14, 380 17, 380 15, H04N 716

Patent

active

047258829

ABSTRACT:
A scrambled video signal processor comprises an amplifier for outputting a noninverted video signal and an inverted video signal, a timing pulse controller for generating first and second timing pulses at a pedestal position in an arbitrary horizontal synchronous signal period of the video signal, and a third timing pulse in an arbitrary video period of the video signal, first and second pedestal clampers for receiving one of the noninverted and inverted video signals from the amplifier and clamping a pedestal level of the arbitrary horizontal synchronous signal period, an offset level controller for receiving the first timing pulse, for DC-restoring to a first level the pedestal position of the horizontal synchronous signal period of the noninverted video signal, and for DC-restoring to a second level, which is different from the first level, the pedestal position of the horizontal synchronous signal period of the inverted signal, a pedestal level controller for DC-restoring to a third level of the other pedestal position of the horizontal synchronous signal period of the inverted video signal in response to the second timing pulse, and a first switch which is switched to select one of the first and second pedestal clampers in response to the third timing pulse.

REFERENCES:
patent: 3396232 (1968-08-01), Hendrickson et al.
patent: 3924059 (1975-12-01), Horowitz
patent: 4075660 (1978-02-01), Horowitz
patent: 4222068 (1980-09-01), Thompson
patent: 4336553 (1982-06-01), den Toonder et al.
patent: 4340906 (1982-07-01), den Toonder et al.
patent: 4598318 (1986-07-01), Robbins
patent: 4651205 (1987-03-01), Crowther
DE Journal-Funkschau, 8/1985-pp. 58 to 61.

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