Scramble circuit to protect data in a read only memory

Details Scramble circuit to protect data in a read only memory Scramble circuit to protect data in a read only memory

1999-01-13

2002-06-18

Hua, Ly V. (Department: 2132)

Cryptography

Particular algorithmic function encoding

Nbs/des algorithm

C380S044000, C380S044000, C380S001000

Reexamination Certificate

active

06408073

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a scramble circuit that can be applied in a microprocessor or a micro-controller with a read only memory built therein to prevent the data stored in the read only memory from being illegally copied and used.
2. Description of the Related Art
In an 8-bit single-chip micro-controller, a scramble circuit for protecting data stored in a read only memory (ROM) is usually structured as a 64-byte or 32-byte key table. However, such a key table will occupy a large area on the chip, thus enlarging the chip size and increasing the production cost. In addition, once the key table is revealed, there also exists a danger that the data stored in the read only memory will be illegally read and copied.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a scramble circuit to protect the data stored in a read only memory. The scramble circuit includes a pseudo random generator and an adder. The pseudo random generator is used to encode the data stored in the read only memory according to an initial value. The adder is used add the encoded data of the pseudo random generator and the data stored in the read only memory to obtain scrambled data. According to the present invention, the scramble circuit only needs a 2-byte key table (initial value) accompanied with a pseudo random generator and an adder, thus greatly shrinking the chip size and lowering the production cost. Because the original data (ROM DATA) can not be predicted, the scrambled data obtained by the pseudo random generator in response to the initial value as well as the original data can hardly be decoded.
It is another object of the present invention to provide a scramble circuit to protect the data stored in a read only memory that utilizes an arithmetic logic circuit (a pseudo random generator and an adder) to encode the data stored in the read only memory according to an initial value, then adds the encoded data and the original data stored in the read only memory to obtain scrambled data. Therefore, no de-scramble circuit can be provided for this scramble circuit, and it is almost impossible to de-scramble the scrambled data.
To realize the above and other objects, the present invention takes both the data stored in the read only memory and the initial value as input variables of the pseudo random generator, then adds the encoded data of the pseudo random generator and the original data stored in the read only memory to obtain the scrambled data. Therefore, no de-scramble circuit can be provided for this scramble circuit, and it is almost impossible to de-scramble the scrambled data.
According to the present invention, the scramble circuit for protecting data stored in a read only memory includes an initial value generator, a shift register, a logic circuit, an adder and a lock circuit. The initial value generator is used to generate an initial value. The shift register is used to selectively load in the initial value and the data stored in the read only memory. The logic circuit is used to process the data stored in the shift register to generate an output transmitted back to the shift register. The adder is used to add the data stored in the read only memory and the data stored in the shift register having the same lengths so as to obtain scrambled data. The lock circuit is used to output or lock the scrambled data according to a lock signal.
In this scramble circuit, the pseudo random generator simultaneously takes the irregular data stored in the read only memory and the initial value of the initial value generator as input variables; therefore, the encoding operation performed is very complicated and dependent on the original data stored in the read only memory.
When the shift register is a 16-bit shift register, the logic circuit can process the data stored in the shift register using a polynomial f(x)=x
15
+x
12
+x
7
+x+1 and transmit the output f(x) back to the zeroth bit of the shift register while the remaining bits are shifted. In this case, x
15
, x
12
, x
7
and x are respectively the fifteenth, twelfth, seventh and first bits of the shift register, and the data stored in the shift register are unchanged after being encoded using an initial value of FFFEH, because f(X)=1, and are changed after being encoded using an initial value ranging from 0000H to FFFEH.
Further, the data stored in the read only memory can be loaded in the shift register to increase the scramble complexity when the data stored in the shift register satisfy a predetermined condition. The adder can add the data in the read only memory and the data stored in the shift register having the same lengths to obtain the scrambled data. Moreover, a lock circuit can be provided to output or lock the scrambled data according to a lock signal.


REFERENCES:
patent: 5515437 (1996-05-01), Katta et al.
patent: 5894517 (1999-04-01), Hutchinson et al.

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