SCR devices with deep-N-well structure for on-chip ESD...

Details SCR devices with deep-N-well structure for on-chip ESD... SCR devices with deep-N-well structure for on-chip ESD...

2001-06-22

2004-07-20

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000

Reexamination Certificate

active

06765771

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a silicon-controlled rectifier, SCR, component with a deep N-well structure. In particular, the present invention relates to an SCR component of an electrostatic discharge (ESD) protection circuit.
2. Description of the Related Art
Electrostatic discharge (ESD) represents one of the main threats to reliability in semiconductor products, especially in scaled-down CMOS technologies. Due to low breakdown voltage of thinner gate oxide in deep-submicron CMOS technologies, an efficient ESD protection circuit must be designed and placed on every input pad to clamp the overstress voltage across the gate oxide of the internal circuit.
Due to the low holding voltage (Vhold, about 1V in CMOS process) of the SCR, power (Power=IESD×Vhold) generated by the SCR device during the ESD stress is less than other ESD protection devices (such as diode, MOS, BJT, or field-oxide device) in CMOS technologies. Therefore, the SCR device can sustain a much higher ESD level within a smaller layout area in the CMOS IC's. Thus, SCR devices have been used as the main ESD-clamped devices in several ESD protection circuits. In traditional CMOS technologies, well regions and heavy-doped diffusions are laterally deposited on a substrate to form an SCR device also known as lateral SCR (LSCR). The traditional input ESD protection circuit with the LSCR device is shown in
FIG. 1
a
, and the device structure of the SCR device in CMOS process is shown in
FIG. 1
b
. The PNPN structure of the LSCR is formed by the p+ diffusion
10
, the N-type well
12
, the P-type substrate
14
and the N+ diffusion
16
. The typical I-V curve on the SCR device in CMOS process is shown in
FIG. 1
c
. The LSCR devices in
FIG. 1
b
have a trigger voltage V
trigger
approximately equal to the breakdown voltage of the P-N junction between the N-well
12
and the p-substrate
14
, about 30~40V, which is generally greater than the gate-oxide breakdown voltage (15~20 volt) of CMOS devices. Therefore, SCR devices need a secondary protection ESD circuit (as the resistor and MESD shown in
FIG. 1
a
) to ensure overall ESD protection.
In order to effectively protect output buffers by using SCR devices, an LVTSCR (low-voltage triggering SCR) device has been invented to lower the trigger voltage of the SCR device. The typical design for output ESD protection circuits with LVTSCR device is shown in
FIG. 2
a
, and the device structure of the LVTSCR is shown in
FIG. 2
b
. The I-V characteristics of the LVTSCR device in the submicron CMOS technology is illustrated in
FIG. 2
c
. In
FIG. 2
c
, the trigger voltage of the LVTSCR may be decreased to about 10V. In previous designs using SCR or LVTSCR devices, the body of the SCR or LVTSCR devices is the common p-substrate
14
, which is commonly grounded, as shown in
FIGS. 1
b
and
2
b
. Therefore, they serve only as routes from the input/output (I/O) pads to VSS or VDD power lines as I/O ESD protection circuits, or from VDD to VSS as a VDD-to-VSS ESD clamp circuit.
To provide high-noise immunity in analog or RF IC, a CMOS process often supports an additional deep N-well structure to isolate the P-well from the grounded p-substrate. Because noise generated from the digital circuits is often coupled into the common P-type substrate, signals in the high-performance analog circuits or the critical DRAM memory cells are easily affected by the coupled noises from the P-type substrate. To overcome the noise issue, a CMOS process often provides an additional deep N-well structure to isolate NMOS in the memory array from the periphery circuits. However, once the noise triggers the SCR and LVTSCR in
FIGS. 1
a
and
2
a
, the signal voltage on the I/O pad will be latched up and the actual signals will not be detected correctly.
SUMMARY OF THE INVENTION
A novel object of the present invention is to provide a new SCR structure having the ability to be stacked in series.
Another object of the present invention is to protect IC from ESD stress at the input, output, or power pads and free from the latch-up issue.
According to the object described above, the present invention provides a novel ESD protection component, located on a P-substrate coupled to a relatively low-voltage power source. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer (as an anode of the SCR), an N-type layer (as a cathode of the SCR) a first N-well and a first P-well. The first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer. The first P-well is contacted with the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, for isolating the electric connection between the P-substrate and the first P-well.
The present invention further provides an ESD protection circuit coupled between a first connection pad and a second connection pad. The ESD protection circuit comprises an ESD protection component having an anode and a cathode. The ESD protection component is located on a P-substrate coupled to a relatively low-voltage power source and comprises a lateral SCR and a deep N-well. The lateral SCR comprises: a P-type layer, as the anode of the SCR; an N-type layer, as the cathode of the SCR; a first N-well, located between the P-type layer and the N-type layer and contacted with the P-type layer; and a first P-well, contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate for isolating the electric connection between the P-substrate and the first P-well. Wherein during an ESD event, the anode and the cathode are respectively connected to the first connection pad and the second connection pad.
The advantage of the present invention is that the deep N-well equivalently increases the resistor between the first p-well and the p-substrate. Moreover, after an appropriate design, the electric connection between the P-substrate and the first P-well is isolated. A plurality of the ESD components in the present invention can be connected to increase the total holding voltage, thereby preventing the latch-up event.


REFERENCES:
patent: 5728612 (1998-03-01), Wei et al.
patent: 5856214 (1999-01-01), Yu
patent: 5959332 (1999-09-01), Ravanelli et al.
patent: 6365940 (2002-04-01), Duvvury et al.

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