SCR circuit with a high trigger current

Details SCR circuit with a high trigger current SCR circuit with a high trigger current

1998-12-08

2001-06-12

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Device protection

C257S109000, C257S162000, C257S356000, C257S357000, C257S362000

Reexamination Certificate

active

06246079

ABSTRACT:

GENERAL DESCRIPTION OF THE INVENTION
The present invention relates to an ESD protection circuit, and in particular, to an SCR circuit with a high trigger current which can avoid being triggered due to external noise or unexpected interference, thereby ensuring normal operations of the circuits to be protected.
BACKGROUND TO THE INVENTION
FIG. 1A
(Prior Art) is a schematic structure of a conventional ESD protection circuit according to U.S. Pat. No. 5,012,317. In this case, a ESD protection circuit
20
is provided between a pad
12
to be protected and a reference ground, and is formed of a four-layer semiconductor device. An N-type layer
24
is formed adjacent to a P-type layer
22
, a P-type layer
26
is formed adjacent to the N-type layer
24
, and an N-type layer
28
is formed adjacent to the P-type layer
26
. Further, the P-type layer
22
is connected to the pad
12
to be protected, and the N-type layer
28
is connected to the reference ground. A PN junction
30
is formed between the P-type layer
22
and the N-type layer
24
, a PN junction
32
is formed between the N-type layer
24
and the P-type layer
26
, and a PN junction
34
is formed between the P-type layer
26
and the N-type layer
28
. Usually, a circuit such as ESD protection circuit
20
(four-layer semiconductor device) is called a silicon controlled rectifier (SCR) circuit.
FIG. 1B
(Prior Art) is an equivalent circuit of the ESD protection circuit in FIG.
1
A. As shown in
FIG. 1B
, a PNP transistor
36
has an emitter connected to the pad
12
to be protected, a base connected to a collector of an NPN transistor
38
, and a collector connected to a base of the NPN transistor
38
. The NPN transistor
38
has an emitter connected to the reference ground. Further, the emitter-base junction of the PNP transistor
36
is the PN junction
30
, the collector-base junction of the NPN transistor
38
(or the PNP transistor
36
) is the PN junction
32
, and the emitter-base junction of the NPN transistor
38
is the PN junction
34
. A resistor
40
is provided between the base of the NPN transistor
38
and the reference ground to increase the base current of the NPN transistor
38
when the collector current of the PNP transistor
36
is increased. Moreover, a resistor
42
is provided between the pad
12
and the base of the PNP transistor
36
to decrease the current gain of the PNP transistor
36
.
As shown in
FIG. 1A
, when a positive impulse suddenly occurs at the base of the NPN transistor
38
, the NPN transistor
38
is turned on with its collector voltage lowered and a current running through the collector-emitter junction of the NPN transistor
38
. At this time, the PNP transistor
36
is active with its collector current running through the base of the NPN transistor
38
, therefore, the SCR circuit will positively regenerate and cause the SCR circuit to remain on, even after the impulse at the base of the NPN transistor
38
fades away, until the collector current of the PNP transistor
36
is insufficient to drive on the NPN transistor
38
.
FIG. 2
(Prior Art) is a schematic cross sectional diagram showing the SCR circuit in FIG.
1
A and
FIG. 1B
in a semiconductor substrate. An N-well
46
, as the N-type layer
24
in
FIG. 1A
, is defined in the lightly doped P-type semiconductor substrate
44
. The PN junction
32
is formed between the N-well
46
and the P-type semiconductor substrate
44
. A P-type region
48
, as the P-type layer
22
in
FIG. 1A
, is defined on P-type semiconductor substrate
44
. The PN junction
30
is formed between the P-type region
48
and the N-well
46
. The P-type region
48
is connected to the pad
12
to be protected. An N-type region
50
is defined in the N-well
46
to provide resistive connect between the pad
12
and the N-well
46
, so as to inversely turn on the PN junction
32
when negative transients.
Moreover, an N-type region
52
, as the N-type layer
28
in
FIG. 1A
, is provided in the P-type semiconductor substrate
44
outside the N-well
46
. The PN junction
34
is formed between the N-type region
52
and the P-type semiconductor substrate
44
. A heavily doped P-type region
54
is formed in the P-type semiconductor substrate
44
outside the N-well
46
to provide a low resistance area, connected to the resistor
40
formed of the P-type semiconductor substrate
44
, and connected to the N-type region
52
and the reference ground.
FIG. 3
(Prior Art) is a schematic diagram showing the current-voltage (I-V) characteristics of the SCR circuit in FIGS.
1
A~
1
B and FIG.
2
. When the voltage of the pad
12
gets smaller than an initial voltage V
T
, which is usually ranged between 30V and 50V, the circuits to be protected perform normal operations as the segment A of FIG.
3
. At this time, the PNP transistor
36
and the NPN transistor
38
of the SCR circuit are shut down (the current running through these two transistors approaches zero) without affecting the normal operations of the circuits to be protected. When the voltage of the pad
12
, such as ESD noise or a large signal, exceeds the initial voltage V
T
and is inputted to the SCR circuit, the PNP transistor
36
is first turned on and absorbs a part of the current generated at the pad
12
due to ESD noise or a large signal as the segment B of FIG.
3
. At this time, the NPN transistor
38
is shut down, and the collector current of the PNP transistor
36
is grounded through the resistor
40
. After the voltage across the resistor
40
increases to exceed a threshold voltage V
TH
of the NPN transistor
38
, the NPN transistor
38
of the SCR circuit is also turned on, and is structured accompanying the PNP transistor
36
as a positive regeneration circuit as the segment C of FIG.
3
. At this time, the equivalent impedance of the SCR circuit approaches zero, so most of the current generated at the pad
12
can be absorbed by the SCR circuit due to this low impedance. As a result, the voltage of the pad
12
can be greatly decreased and the circuits to be protected can avoid damage caused by ESD noise or large currents.
However, because this SCR circuit is easily triggered by low currents, such as overshooting or undershooting, the circuit to be protected may also be mistakenly interrupted even under normal operations.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a SCR circuit with a high trigger current, which can avoid being triggered due to external noise or unexpected interference, thereby ensuring normal operations of the circuits to be protected.
According to a first aspect of the present invention, the SCR circuit is provided in the P-type semiconductor substrate with an N-well formed therein. In the P-type semiconductor substrate, there is provided a P-type region and an N-type region. In the N-well, there is provided another P-type region and another N-well. The P-type region and the N-type region in the P-type region, as well as another P-type region formed between the P-type semiconductor substrate and the N-well, are connected to serve as a cathode of the SCR circuit, while the P-type region and the N-type region in the N-well are connected to serve as an anode of the SCR circuit. When the voltage of the pad to be protected increases, the transistor constructed with the anode, the N-well and the P-type region formed between the P-type semiconductor substrate and the N-well is first turned on, absorbing a part of the current generated at the pad due to ESD noise or other currents and decreasing the voltage of the pad to some extent. When the voltage keeps increasing, the transistor constructed with the anode, the N-well and the P-type semiconductor substrate is also turned on, absorbing most of the current generated at the pad and greatly lowering the voltage thereof.
According to a second aspect of the present invention, the SCR circuit is provided in the P-type semiconductor substrate with an N-well formed therein. An N-type region is defined in the P-type semiconductor substrate. Another N-type region and

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