Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Patent
1996-12-31
1999-10-26
Oberley, Alvin E.
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
711144, G06F 900
Patent
active
059744383
ABSTRACT:
A computer system comprising at least one processor and associated cache memory, and a plurality of registers to keep track of the number of cache memory lines associated with each process thread running in the computer system. Each process thread is assigned to one of the plurality of registers of each level of cache that is being monitored. The number of cache memory lines associated with each process thread in a particular level of the cache is stored as a number value in the assigned register and will increment as more cache memory lines are used for the process thread and will decrement as less cache memory lines are used. The number value in the register is defined as the "process thread temperature." Larger number values indicate warmer process thread temperature and smaller number values indicate cooler process thread temperature. Process thread temperatures are relative and indicate the cache memory line usage by the process threads running in the computer system at a particular level of cache. By keeping track or "score" of the number values (temperatures) in each of these registers called "scoreboard registers," the scheduler algorithm of the computer operating system may objectively determine the most advantageous order for the process threads to run and which of the processors in a multi-processor system should execute these process threads. A scoreboard register may be reassigned to a new process thread when its associated process thread has been discontinued.
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Cherubin Yveste G.
Compaq Computer Corporation
Frohwitter Paul Katz
Oberley Alvin E.
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