Schottky-transistor-logic

Details Schottky-transistor-logic Schottky-transistor-logic

1977-05-20

1980-01-08

Larkins, William D.

Metal treatment

Stock

Ferrous

357 15, 357 46, 357 50, 357 91, 357 92, 148 15, H01L 2704, H03K 1908

Patent

active

041830369

ABSTRACT:
A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other conductivity type is located in the epitaxial layer in a plane spaced below the outer surface of said epitaxial layer and lying substantially parallel thereto. A load transistor and an output transistor are formed by constructing the arrangement so that the buried layer provides the base of the load transistor and the emitter of the output transistor. The emitter of the load transistor is provided by a portion of the epitaxial layer which lies below the deep-implanted doped zone. The collector of the load transistor and the base of the output transistor are provided by the portion of the epitaxial layer which lies above the deep-implanted zone. A Schottky electrode on the outer surface of the epitaxial layer provides the collector of the output transistor. A plurality of Schottky diodes are also formed in a portion of the epitaxial layer which possess a lower Schottky barrier than the Schottky electrode of the output transistor.

REFERENCES:
patent: 3823353 (1974-07-01), Berger et al.
patent: 3909807 (1975-09-01), Fulton
patent: 3922565 (1975-11-01), Berger et al.
patent: 3961351 (1976-06-01), Blatt
patent: 3987310 (1976-10-01), Peltier et al.
patent: 4035664 (1977-07-01), Berger et al.
patent: 4053925 (1977-10-01), Burr et al.
Berger et al., "Schottky Transistor Logic", IEEE ISSCC, Digest of Technical Papers, pp. 172-173 (Feb. 1975).
Blatt et al., IEEE IEDM, Technical Digest, (Dec. 1974), pp. 511-514.

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