Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier
Reexamination Certificate
2003-05-15
2004-06-01
Tran, Minh-Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
C257S473000, C257S474000, C257S477000, C257S486000
Reexamination Certificate
active
06744111
ABSTRACT:
TECHNICAL FIELD
This application relates to a semiconductor device, specifically, a semiconductor transistor device suitable for analog and digital circuits.
BACKGROUND OF THE INVENTION
For more than 30 years, the integrated circuit industry has followed a dramatic path of shrinking device dimensions and increasing chip sizes, resulting in steadily increased performance and increased functionality. New generations of devices have appeared in every two to three years, following the so called “Moore's Law”, with each new generation device approximately doubling logic circuit density, increasing performance by about 40%, and quadrupling the memory capacity comparing to the previous generation. The consistency of this advancement has led to an expectation that faster and more powerful chips will continue to be introduced on the same schedule in the foreseeable future.
The silicon semiconductor industry has charted a course for itself over the next 15 years, which attempts to continue the density and performance improvements of the past 40 years. The International Technology Roadmap for Semiconductor (ITRS) has forecasted that this device scaling and increased functionality scenario to continue until 2013, at which point the minimum feature size is projected to reach 32 nm and a single chip is expected to contain more than 10
11
components.
Most of the historic trend has been achieved with the same basic switching element (the MOS transistor) and the same basic circuit topology (CMOS) based on a limited number of materials (Si, SiO
2
, Al, Si
3
N
4
, TiSi
2
, TiN, W, primarily). While very substantial human and financial resources invested have improved manufacturing practices over the past 40 years, the device structures of 30-40 years ago are still quite recognizable in today's IC industry.
A large part of the success of the MOS transistor is due to the fact that it can be scaled to increasingly smaller dimensions, which results in higher performance. The ability to improve performance consistently while decreasing power consumption has made CMOS architecture the dominant technology for integrated circuits. The scaling of the CMOS transistor has been the primary factor driving improvements in microprocessor performance. The transistor delay has decreased by more than 30% per technology generation resulting in a doubling of microprocessor performance every two years. In order to maintain this rapid rate of improvement, aggressive engineering of the MOS transistor is required.
Conventional scaling of gate oxide thickness, source/drain extension (SDE) junction depths, and the gate lengths has enabled MOS gate dimensions to be reduced from 10 &mgr;m in the 1970's to a present day size of 0.1 &mgr;m. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow junctions with low resistivity need to be developed.
Silicon technology has reached the point at which significant innovations will be required to circumvent the challenges associated with continued MOSFET scaling. Current performance scaling trends will not continue past the 0.1 &mgr;m device technologies by using traditional scaling methods. Fundamental limits in SiO
2
scaling due to tunneling current, in SDE junction depths due to large increases in external resistance, and in well engineering due to leakage constraints are currently being reached. The most apparent challenges are gate insulators with high dielectric constant and ultra-shallow junctions with low sheet resistance. At present, there are no known solutions for the MOS device technologies to continue the performance trends seen in the last 20 years. Practical and fundamental limits are being approached and substantial changes to device technologies and structures are required.
Aggressive scaling of silicon integrated devices in the deep sub-micron range presents considerable challenges to device engineers. Device performance must be preserved as much as possible, when going from one generation to the next, while the devices must be manufacturable and cost-effective. As the milestone of 32-nm gate length MOSFET is approached, alternative device structures are being considered that might allow the continuation of scaling trends when physical limits of conventional MOSFETs are eventually reached. There is therefore a need to provide a device structure to enable the continued downward scaling of transistor dimensions into the 21st century.
SUMMARY OF INVENTION
Implementations of the system may include one or more of the following. The invention system generally includes a three-terminal semiconductor transistor device, comprising:
a) a base region formed by a semiconductor material, the base region being in contact with a first electric terminal;
b) a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region, the conductive emitter region being in contact with a second electric terminal; and
c) a conductive collector region in contact with the semiconductor base region, forming a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region, the conductive collector region being in contact with a third electric terminal,
wherein the tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the semiconductor base region.
In another aspect, the invention system includes a three-dimensional three-terminal semiconductor device, comprising:
a) a first insulating substrate layer; and
b) a second substrate layer formed above the first insulating substrate layer, comprising
i) a base region formed by a semiconductor material, the base region being in contact with a first electric terminal;
ii) a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region, the conductive emitter region being in contact with a second electric terminal; and
iii) a conductive collector region in contact with the semiconductor base region, forming a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region, the conductive collector region being in contact with a third electric terminal,
wherein the tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the semiconductor base region.
In still another aspect, the invention system includes a three-dimensional three-terminal semiconductor device, comprising:
a) a first electric terminal formed in a lower substrate layer;
b) a middle substrate layer, comprising
i) a lower conductive region in contact with the first electric terminal in the lower substrate layer,
ii) a middle semiconductor region in contact with the lower conductive region in the lower substrate layer forming a first Schottky barrier junction at the interface of the middle semiconductor region and the lower conductive region, such middle semiconductor region being in contact with a second electric terminal; and
iii) an upper conductive region in contact with the middle semiconductor region forming a second Schottky barrier junction at the interface of the upper conductive region and the middle semiconductor region, such upper conductive region being separated from the lower conductive region by the middle semiconductor region; and
c) a third electric terminal formed over the middle substrate layer, the third electric terminal being in contact with the upper conductive region in the middle substrate layer,
wherein the tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the middle semiconductor region.
The new device structure
Tran Minh-Loan
Wen Xin
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