Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
2002-12-31
2004-02-17
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S192000, C257S347000, C257S349000, C438S149000, C438S570000
Reexamination Certificate
active
06693294
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the priority of Korean Patent Application No. 2002-47506, filed on Aug. 12, 2002 in the Korean Intellectual Property Office, which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a transistor and a method of fabricating the same, and more particularly, to a Schottky barrier tunnel transistor (hereinafter, referred to as “SBTT”) using a Schottky barrier formed between metal and a semiconductor, and a method of fabricating the same.
2. Description of the Related Art
Advances in the techniques of fabricating semiconductor devices result in the development of a transistor having a short channel of 100 nm or less. Therefore, the characteristics of a semiconductor device, which operates according to the laws of classic electrodynamics, are now governed by quantum mechanics. In this case, a leakage current, however, is extremely increased due to short channel effect in a transistor. Thus, there is a need to prevent a short channel effect from occurring in such a transistor.
To suppress the occurrence of the short channel effect, junction depth of source and drain regions must be within the range from a quarter to one third of the channel length of a transistor. Extensive research is continuously conducted to reduce the junction depth of source and drain regions with low accelerating voltage, using a general ion implantation method, but it is almost impossible to regularly and shallowly form the junction depth to 30 nm or less. Meanwhile, a reduction in the junction depth results in an increase in parasitic resistance. For instance, if a doping concentration is 1E19 cm
−3
and junction depth is 10 nm, a sheet resistance value exceeds more than 500 &OHgr;/□ and a signal delay would be caused.
Accordingly, an increase in the permittivity of a gate oxide layer, as well as a shallow junction depth, is required to suppress the occurrence of the short channel effect. To increase the permittivity of a gate oxide layer, a rare-earth oxide layer is used as a better alternative than a silicon oxide layer. However, the rare-earth oxide layer is thermally unstable and thus is not proper to be processed at a high temperature, unlike the silicon oxide layer. For the use of the rare-earth oxide layer, a process temperature is required to be remarkably reduced when fabricating a semiconductor device, but a great reduction in the process temperature will place a limit on the thermal treatment for doping activation and recovery of damaged crystals.
A SBTT is known as a transistor that has shallow junction depth and enables a gate oxide layer with high permittivity. Shallow junction depth is considered the most important factor in scaling down a metal-oxide-semiconductor field effect transistor (MOSFET). The SBTT is made by replacing source and drain regions of the MOSFET with metal or silicide, in which a sheet resistance value is reduced from one tenth to one fiftieth of that of a general transistor. Therefore, the operational speed of the SBTT is improved, and the channel length is reduced to 35 nm or less. Also, ion implantation is not carried out when fabricating the SBTT, and therefore the subsequent thermal treatment is not needed. For this reason, the SBTT is compatible with fabricating a transistor adopting a gate oxide layer of high permittivity. Further, the SBTT is fabricated using a lower thermal process than a general transistor and thus fabrication of the SBTT is compatible with a process of fabricating a transistor having a metallic gate electrode.
In general, a bulk silicon substrate is mainly used in fabricating a SBTT or conducting research into the operational characteristics of the SBTT. However, the use of a bulk silicon substrate causes a great number of silicon atoms to diffuse into the suicide during the formation of silicide source and drain regions, thereby causing. a lot of vacancies in the crystalline bulk silicon substrate. The vacancies are generally densely formed in a space charge region and act as interface impurities that generate leakage current.
To prevent the formation of vacancies, it is suggested that the SBTT be fabricated with a silicon-on-insulator (SOI) substrate. However, in the SBTT formed on the SOI substrate, an interface between a buried oxide layer and an SOI layer becomes a path through which a leakage current is generated.
SUMMARY OF THE INVENTION
To solve the above problem, it is one aspect of the present invention to provide a SBTT in which generation of short channel effect and a leakage current are prevented.
It is another aspect of the present invention to provide a method of fabricating such a SBTT.
To achieve one aspect of the present invention, there is provided a Schottky barrier tunnel transistor (SBTT) including a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove.
Preferably, the SOI layer is formed to a thickness of about 50 nm or less.
The conductive layer and the gate may be formed of doped polysilicon. Otherwise, the conductive layer may be formed of doped polysilicon and the gate may be formed of silicide.
An insulating spacer and a hard mask layer may be further formed on sidewalls of the gate and on the gate, respectively.
Preferably, the bottoms of the source and drain regions contact the buried oxide layer.
As mentioned above, the SBTT according to the present invention is fabricated using a Schottky barrier. The Schottky barrier is formed between metal and a semiconductor and is made by forming silicide source and drain regions on a thin SOI layer. The SOI layer is formed to an ultra-thin thickness to minimize leakage current, and a channel in the SOI layer below a gate is completely wrapped by the gate and a conductive layer, thereby improving the operational characteristics of the SBTT.
To achieve another aspect of the present invention, there is provided a method of fabricating an SBTT, including making a substrate on which a base substrate layer, a buried oxide layer, and an ultra-thin SOI layer are sequentially formed; patterning the SOI layer to define two wide regions, as source and drain regions, and a narrow channel region between the two wide regions; forming a groove by removing a portion of the buried oxide layer that contacts the channel region; thermally oxidizing the remaining SOI layer to form an insulating layer, the insulating layer wrapping the channel region; depositing a conductive material for a gate on the insulating layer while filling the groove with the conductive material; patterning the conductive material and the insulating layer to form a gate and a gate oxide layer across the channel region, the gate and the gate oxide layer being formed to be wider than the groove; and forming source and drain regions on the two wide regions using silicide.
The SOI layer is formed to a thickness such that an electric field controlled by the gate can completely control the channel region.
Forming a groove includes forming a photoresist on the remaining SOI layer; performing exposure and development on the photoresist to form an opening that is wider than the channel region; removing a predetermined thickness of the buried oxide layer exposed via the opening and having an etch selectivity with respect to the SOI layer; and removing the photoresist entirely.
Forming the gate and the gate oxide layer includes forming a hard mask layer on the conductive material to be wider than the groove and across the channel region; and patterning the conductive material and the insulating layer using the hard mask layer.
Forming the source and drain regions includes depositing a refractory metal layer on the
Cheong Woo-Seok
Cho Won-Ju
Jang Moon-Gyu
Lee Seong-Jae
Park Kyoung-Wan
Crane Sara
Electronics and Telecommunications Research Institute
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