Schmitt trigger circuit using MOS transistors and having constan

Details Schmitt trigger circuit using MOS transistors and having constan Schmitt trigger circuit using MOS transistors and having constan

1983-07-25

1986-01-07

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307359, 307279, 307603, H03K 3295

Patent

active

045635943

ABSTRACT:
An input CMOS inverter comprises a complementary pair of first and second MOS transistors having their gates connected together to receive an input signal, and a buffer circuit connected between drains of the first and second MOS transistors. The buffer circuit is preferably an analog switch circuit having a complementary pair of third and fourth MOS transistors responsive to the input signal and connected in parallel. In response to a potential variation caused at the drain of one of the first and second transistors, the buffer circuit causes a potential variation at the drain of the other transistor after a delay. There is provided a second MOS inverter having a complementary pair of fifth and sixth MOS transistors with their gates connected to the drains of the first and second transistors, respectively. A feedback circuit is connected to the output of the second inverter to suppress the potential variation at the drains of the first and second transistors. The feedback circuit preferably includes a third inverter and a complementary pair of seventh and eighth MOS transistors connected to the drains of the first and second transistors, respectively, and controlled by the third inverter.

REFERENCES:
patent: 3740580 (1973-06-01), Spies
patent: 3904888 (1975-10-01), Griffin et al.
patent: 4295062 (1981-10-01), Mihalich et al.
patent: 4369381 (1983-01-01), Okamoto et al.
patent: 4438352 (1984-03-01), Mardkha
patent: 4464587 (1984-08-01), Suzuki et al.
Patent Abstracts of Japan, Nov. 27, 1979, vol. 3, No. 143.

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