Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2000-06-30
2004-12-21
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Reexamination Certificate
active
06834262
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacturing processes and, in particular, to a scheme for improving the accuracy of integrated circuit pattern simulation by first simulating a photolithographic mask of the circuit, followed by image simulation of that mask on a wafer.
BACKGROUND
As shown in
FIG. 1
, during the manufacture of integrated circuits, various circuit features are patterned in photoresist layers
10
that are disposed over a semiconductor wafer or die
12
by exposing the photoresist to radiation (e.g., various wavelengths of light)
14
through a mask or reticle
16
. The mask
16
is created from an as-drawn design for the circuit features produced by a circuit designer using conventional software tools. However, the image of a photolithographic mask
16
printed on a silicon wafer
12
(i.e., on a photoresist layer
10
) is usually significantly distorted with respect to the drawn design, due to light refraction effects. To compensate for these distortions, corner rounding and proximity effects of the design need to be predicted by pattern simulation in a process referred to as optical proximity correction (OPC). OPC involves the use of software simulation tools to convert the drawn design into an aerial image of light intensity contours, which correspond to the actual photoresist patterns that will be printed on the wafer. The drawn layout may then be corrected, for example by adding sublithographic features such as serifs, with subsequent iterations of the simulation (manual or automated) providing feedback to achieve a desired final shape.
In this simulation process, it is usually assumed that the photolithographic mask is an ideal reproduction of the drawn pattern. However, mask making processes have limited accuracy due to the limitations of finite e-beam spot sizes and mechanical limitations of photoresist development and etching processes. Consequently, small serifs used for correction of proximity effects may not be adequately reproduced in the masks. Disregarding such mask errors in the process of correcting the drawn circuit feature layouts may result in substantial deviations from the desired image when the image is printed on a wafer. Thus, what is needed is a process to ensure that the masks are produced as accurately as possible.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present scheme, a mask simulation process is introduced into a conventional OPC procedure, prior to simulation of a photoresist pattern. Reticle simulation may be achieved using very short wavelengths of light as compared to the mask feature size. Alternatively, reticle simulation may be made through adjustments in a computer aided design process.
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Balasinski Artur E.
Coburn Dianna L.
Hong Dongsung
Kim Keeho E.
Cypress Semiconductor Corporation
Evan Law Group LLC
Teska Kevin J.
Thangavelu Kandasamy
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