Scheme for determining internal mode using MCLK frequency...

Details Scheme for determining internal mode using MCLK frequency... Scheme for determining internal mode using MCLK frequency...

2007-03-20

2007-03-20

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S123000, C341S061000

Reexamination Certificate

active

10891944

ABSTRACT:
A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

REFERENCES:
patent: 5532556 (1996-07-01), Anderson et al.
patent: 5689534 (1997-11-01), Anderson et al.
patent: 6184905 (2001-02-01), Hartog
patent: 6492928 (2002-12-01), Rhode et al.
patent: 6531975 (2003-03-01), Trotter et al.
patent: 6754295 (2004-06-01), Hartnett

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