Schematic compiler for a multi-format high speed multiplier

Details Schematic compiler for a multi-format high speed multiplier Schematic compiler for a multi-format high speed multiplier

1990-08-09

1995-05-02

Mai, Tan V.

Boots, shoes, and leggings

364489, G06F 752

Patent

active

054125910

ABSTRACT:
A multiplier compiler produces a schematic of a high-speed, multi-format multiplier. The compiler receives user information which indicates design preferences. Based on the user information the compiler can select the format of numbers which the multiplier will multiply and/or select a type of adder with which to implement the final adder row of the multiplier. The compiler generates user readable schematics of the multiplier. The schematic displays discrete components of the multiplier arranged in locations which show to the user the flow of logic of the circuit. Additionally, the compiler generates test vectors.

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