Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2005-09-06
2005-09-06
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S351000, C370S231000, C370S360000, C370S361000, C379S271000, C379S272000
Reexamination Certificate
active
06940851
ABSTRACT:
A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.
REFERENCES:
patent: 5495476 (1996-02-01), Kumar
patent: 6157643 (2000-12-01), Ma
patent: 6810031 (2004-10-01), Hegde et al.
N. W. McKeown, “Scheduling Algorithms for Input-Queued Cell Switches,” PhD Thesis, University of California at Berkeley, (1995).
C. Y. Lee and A. Y. Oruç, “A Fast Parallel Algorithm for Routing Unicast Assignments in Benes Networks,”IEEE Trans. on Parallel and Distributed Sys., vol. 6, No. 3, pp. 329-334 (Mar. 1995).
T. T. Lee and S-Y Liew, “Parallel Routing Algorithms in Benes-Clos Networks,”Proc. IEEE INFOCOM '96, pp. 279-286 (1996).
N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick and M. Horowitz, “Tiny-Tera: A Packet Switch Core,”IEEE Micro., pp. 26-33 (Jan.-Feb. 1997).
T. Chaney, J. A. Fingerhut, M. Flucke, J. S. Turner, “Design of a Gigabit ATM Switch,”Proc. IEEE INFOCOM '97, pp. 2-11 (Apr. 1997).
F. M. Chiussi, J. G. Kneuer, and V. P. Kumar, “Low-Cost Scalable Switching Solutions for Broadband Networking: The ATLANTA Architecture and Chipset,”IEEE Commun. Mag., pp. 44-53 (Dec. 1997).
J. Turner and N. Yamanaka, “Architectural Choices in Large Scale ATM Switches,”IEICE Trans. Commun., vol. E81-B, No. 2, pp. 120-137 (Feb. 1998).
H. J. Chao and J-S Park, “Centralized Contention Resolution Schemes for a Large-Capacity Optical ATM Switch,”Proc. IEEE ATM Workshop '97, pp. 11-16 (Fairfax, VA, May 1998).
G. Nong, J. K. Muppala and M. Hamdi, “Analysis of Nonblocking ATM Switches with Multiple Input Queues,”IEEE/ACM Transactions on Networking, vol. 7, No. 1, pp. 60-74 (Feb. 1999).
N. McKeown, “The iSLIP Scheduling Algorithm for Input-Queued Switches,”IEEE/ACM Transactions on Networking, vol. 7, No. 2, pp. 188-201 (Apr. 1999).
A. Smiljanić, R. Fan and G. Ramamurthy, “RRGS-Round-Robin Greedy Scheduling for Electronic/Optical Terabit Switches,”Global Telecommunications Conference-Globecom '99, pp. 1244-1250 (May 1999).
N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, “Achieving 100% Throughput in an Input-Queued Switch,”IEEE Trans. on Communications, vol. 47, No. 8, pp. 1260-1267 (Aug. 1999).
E. Oki, N. Yamanaka, Y. Ohtomo, K. Okazaki and R. Kawano, “A 10-Gb/s (1.25 Gb/s×8) 4×2 0.25-μm CMOS/SIMOX ATM Switch Based on Scalable Distributed Arbitration,”IEEE J. of Solid-State Circuits, vol. 34, No. 12, pp. 1921-1934 (Dec. 1999).
N. Yamanaka, E. Oki, S. Yasukawa, R. Kawano and K. Okazaki, “OPTIMA: Scalable, Multi-Stage, 640-Gbit/s ATM Switching System Based on Advanced Electronic and Optical WDM Technologies,”IEICE Trans. Commun., vol. E83-B, No. 7, pp. 1488-1496 (Jul. 2000).
J. Chao, “Saturn: A Terabit Packet Switch Using Dual Round-Robin,”IEEE Communications Magazine, pp. 78-84 (Dec. 2000).
G. Nong and M. Hamdi, “On the Provision of Quality-of-Service Guarantees for Input Queued Switches;”IEEE Commun. Mag., pp. 62-69 (Dec. 2000).
E. Oki, Z. Jing, R. Rojas-Cessa, J. Chao, “Concurrent Round-Robin Dispatching Scheme in a Clos-Network Switch,”IEEE ICC 2001, pp. 106-112 (Jun. 2001).
E. Oki, R. Rojas-Cessa and H. J. Chao, “PCRRD: A Pipeline-Based Concurrent Round-Robin Dispatching Scheme for Clos-Network Switches,” pp. 1-18.
A. Smiljanić, “Flexible Bandwidth Allocation in Terabit Packet Switches,” pp. 233-239.
Chao Hung-Hsiang Jonathan
Oki Eiji
Rojas-Cessa Roberto
Chin Wellington
Jain Raj
Pokotylo John C.
Polytechnic University
Straub & Pokotylo
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