Scheduling the dispatch of cells in multistage switches

Details Scheduling the dispatch of cells in multistage switches Scheduling the dispatch of cells in multistage switches

2007-02-06

2007-02-06

Nguyen, Chau (Department: 2616)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S412000

Reexamination Certificate

active

09851461

ABSTRACT:
A multiple phase cell dispatch scheme, in which each phase uses a simple and fair (e.g., round robin) arbitration methods, is described. VOQs of an input module and outgoing links of the input module are matched in a first phase. An outgoing link of an input module is matched with an outgoing link of a central module in a second phase. The arbiters become desynchronized under stable conditions which contributes to the switch's high throughput characteristic. Using this dispatch scheme, a scalable multiple-stage switch able to operate at high throughput, without needing to resort to speeding up the switching fabric and without needing to use buffers in the second stage, is possible. The cost of speed-up and the cell out-of-sequence problems that may occur when buffers are used in the second stage are therefore avoided.

REFERENCES:
patent: 5367520 (1994-11-01), Cordell
patent: 5689506 (1997-11-01), Chiussi et al.
patent: 6072772 (2000-06-01), Charny et al.
patent: 6154459 (2000-11-01), Wicklund
patent: 6285679 (2001-09-01), Dally et al.
patent: 6625121 (2003-09-01), Lau et al.
patent: 6747971 (2004-06-01), Hughes et al.
N. W. McKeown, “Scheduling Algorithms for Input-Queued Cell Switches”, PhD Thesis, University of California at Berkeley, (1995).
C. Y. Lee and A. Y. Oruc, “A Fast Parallel Algorithm for Routing Unicast Assignments in Benes Networks”,IEEE Trans. on Parallel and Distributed Sys., vol. 6, No. 3, pp. 329-333 (Mar. 1995).
T. T. Lee and S-Y Liew, “Parallel Routing Algorithms in Benes-Clos Networks”,Proc. IEEE Infocom '96, pp. 279-286 (1996).
N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick and M. Horowitz, “Tiny-Tera: A Packet Switch Core”,IEEE Micro., pp. 26-33 (Jan.-Feb. 1997).
T. Chaney, J. A. Fingerhut, M. Flucke, J. S. Turner, “Design of a Gigabit ATM Switch”,Proc. IEEE Infocom '97, pp. 2-11 (Apr. 1997).
F. M. Chiussi, J. G. Kneuer, and V. P. Kumar, “Low-Cost Scalable Switching Solutions for Broadband Networking: The ATLANTA Architecture and Chipset”,IEEE Commun. Mag., pp. 44-53 (Dec. 1997).
J. Turner and N. Yamanaka, “Architectural Choices in Large Scale ATM Switches”,IEICE Trans. Commun., vol. E81-B, No. 2, pp. 120-137 (Feb. 1998).
H. J. Chao and J-S Park, “Centralized Contention Resolution Schemes for a Large-Capacity Optical ATM Switch”,Proc. IEEE ATM Workshop '97, (Fairfax, VA, May 1998).
N. McKeown, “The iSLIP Scheduling Algorithm for Input-Queued Switches”,IEEE/ACM Transactions on Networking, vol. 7, No. 2, (Apr. 1999).
N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, “Achieving 100% Throughput in an Input-Queued Switch”,IEEE Trans. on Communications, vol. 47, No. 8, pp. 1260-1267 (Aug. 1999).
E. Oki, N. Yamanaka, Y. Ohtomo, K. Okazaki and R. Kawano, “A 10-Gb/s (1.25 Gb/s×8) 4×2 0.25-μm CMOS/SIMOX ATM Switch Based on Scalable Distributed Arbitration”,IEEE J. of Solid-State Circuits, vol. 34, No. 12, pp. 1921-1934 (Dec. 1999).
J. Chao, “Saturn: A Terabit Packet Switch Using Dual Round-Robin”,IEEE Communications Magazine, pp. 78-84, (Dec. 2000).

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