Scheduling technique for software pipelining

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

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Reexamination Certificate

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07962907

ABSTRACT:
An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in instruction scheduling and reduction of hot spots is achieved by evenly distributing such groups of instructions around the schedule for a given loop.

REFERENCES:
patent: 4989131 (1991-01-01), Stone
patent: 5317734 (1994-05-01), Gupta
patent: 5809308 (1998-09-01), Tirumalai
patent: 6038538 (2000-03-01), Agrawal et al.
patent: 6305014 (2001-10-01), Roediger et al.
patent: 6311265 (2001-10-01), Beckerle et al.
patent: 6952816 (2005-10-01), Gupta et al.
patent: 7096438 (2006-08-01), Sivaraman et al.
patent: 2004/0068708 (2004-04-01), Sivaraman et al.
patent: 0481615 (1991-09-01), None
patent: 0481615 (1992-04-01), None
patent: 7021144 (1994-04-01), None
Aleta, et al., “Instruction Replication for Clustered Microarchitectures,” IEEE, 2003.
Park, et al., “Sehwa: A Program For Synthesis of Pipelines,” pp. 454-460, IEEE, 1986.
Park, et al., “Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications,” pp. 356-370, IEEE, 1988.
Codina, J. et al., “A Comparative Study of Modulo Scheduling Techniques,” ICS, pp. 97-106, New York, Jun. 22-26, 2002.
Sanchez, J. et al., “Instruction Scheduling for Clustered VLIW Architectures,” ISSS 2000, IEEE 1080-1082, pp. 41-46, 2000.
Nitezki, P., “Exploiting Data Parallelism in Signal Processing on a Data Flow Machine,” ACM 0884-7495/89/0000/0054, pp. 54-61, 1989.
Akturan, C. et al., “RS-FDRA: A Register Sensitive Software Pipelining Algorithm for Embedded VLIW Processors,” ACM 1-58113-264-2/01/04, 2001.
Zhou, J. et al., “A DAG-Based Partitioning-Reconfiguring Scheduling Algorithm in Network of Workstations,” IEEE Computer Society HPC-Asia 2000, 0-7695-0589-2/00, May 14-17, 2000, pp. 323-326.
Ling, Z. et al, “A Planning-Based Graph Matching Algorithm for Knowledge Structure Retrieval,” Fourth ISPE International Conference, Technomic Publishing Co., Inc., pp. 223-230, Aug. 20, 1997.

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