Electrical computers and digital processing systems: multicomput – Computer-to-computer data modifying
Reexamination Certificate
2006-11-07
2006-11-07
Luu, Le Hien (Department: 2141)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data modifying
C370S466000
Reexamination Certificate
active
07133932
ABSTRACT:
A scheduling circuit of the present invention includes an IP (Internet Protocol) scheduling/format converting section for scheduling input IP packets and converting each of them to ATM (Asynchronous Transfer Mode) cells. The IP scheduling/format converting section includes a plurality of packet FIFOs (First-In First-Out memories). The ATM cells output from each packet FIFO are written to corresponding one of a plurality of cell FIFOs. An ATM scheduling section schedules the ATM cells received from each cell FIFO cell by cell.
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Luu Le Hien
NEC Corporation
Scully , Scott, Murphy & Presser, P.C.
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