Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
2002-12-31
2008-08-19
Fallansbee, John (Department: 2151)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
Reexamination Certificate
active
07415540
ABSTRACT:
Scheduling the processing of threads by scheduling a datagram from an input queue among a plurality of input queues to a thread for processing. The scheduling includes computing an output position in an output queue, communicating with a plurality of threads for processing, and assigning the datagram to one of said plurality of threads for processing. After processing the datagram, the processing thread enqueus the datagram in the output queues at the output position specified by the scheduled output position.
REFERENCES:
patent: 5475682 (1995-12-01), Choudhury et al.
patent: 5515538 (1996-05-01), Kleiman
patent: 5909695 (1999-06-01), Wong et al.
patent: 6338078 (2002-01-01), Chang et al.
patent: 6427161 (2002-07-01), LiVecchi
patent: 6549930 (2003-04-01), Chrysos et al.
patent: 6631422 (2003-10-01), Althaus et al.
patent: 2003/0188300 (2003-10-01), Patrudu
patent: 2005/0132132 (2005-06-01), Rosenbluth et al.
Fallon Michael
Raghunandan Makaran
Chou Alan S
Fallansbee John
Fish & Richardson P.C.
Intel Corporation
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