Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Patent
1997-11-17
2000-07-04
Banankhah, Majid A.
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
709166, G06F 946
Patent
active
060852151
ABSTRACT:
Method and apparatus for avoiding receive livelock and transmit starvation, and for minimizing packet loss and latency in a communication network station. The invention uses a combination of processing threads, polling and, in a preferred embodiment, a judicious use of interrupts, to allocate the use of processing resources fairly among competing functions. Real time processing threads are structured to execute for a preselected maximum time interval, based on numbers of units processed by each thread, and then to yield control to a thread scheduler, which selects and invokes a new thread for execution. Work to be done in the various threads is determined either by polling or by an interrupt system, and then posted to the threads for execution. If interrupts are used, interrupt service routines perform only the minimal processing needed to recognize an interrupt, other interrupt servicing functions being deferred for execution in a processing thread. The thread scheduler operates on a round-robin basis and also selects from at least one general purpose processing thread for functions that are less time critical, the general purpose thread being structured to operate for a selected minimum time, if needed, in a non-preemptable mode, and thereafter in a preemptable mode.
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Ramakrishnan Kadangode K.
Ting Dennis
Vaitzblit Lev
Banankhah Majid A.
Cabletron Systems Inc.
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