Scheduling eligible entries using an approximated finish...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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C370S395410, C370S392000, C370S412000, C370S468000, C370S503000, C709S226000, C709S235000, C709S240000

Reexamination Certificate

active

07599381

ABSTRACT:
Eligible entries are scheduled using an approximated finish delay identified for an entry based on an associated speed group. One implementation maintains schedule entries, each respectively associated with a start time and a speed group. Each speed group is associated with an approximated finish delay. An approximated earliest finishing entry from the eligible schedule entries is determined that has an earliest approximated finish time, with the approximated finish time of an entry being determined based on the entry's start time and the approximated finish delay of the associated speed group. The scheduled action corresponding to the approximated earliest finishing entry is then typically performed. The action performed may, for example, correspond to the forwarding of one or more packets, an amount of processing associated with a process or thread, or any activity associated with an item.

REFERENCES:
patent: 5625625 (1997-04-01), Oskouy et al.
patent: 5864540 (1999-01-01), Bonomi et al.
patent: 5864557 (1999-01-01), Lyons
patent: 5892766 (1999-04-01), Wicki et al.
patent: 6130878 (2000-10-01), Charny
patent: 6337851 (2002-01-01), Charny et al.
patent: 6408005 (2002-06-01), Fan et al.
patent: 6412000 (2002-06-01), Riddle et al.
patent: 6438134 (2002-08-01), Chow et al.
patent: 6453438 (2002-09-01), Miller et al.
patent: 6483839 (2002-11-01), Gemar et al.
patent: 6560230 (2003-05-01), Li et al.
patent: 6643293 (2003-11-01), Carr et al.
patent: 6683884 (2004-01-01), Howard
patent: 6691312 (2004-02-01), Sen et al.
patent: 6715046 (2004-03-01), Shoham et al.
patent: 6778546 (2004-08-01), Epps et al.
patent: 6810426 (2004-10-01), Mysore et al.
patent: 6836475 (2004-12-01), Chaskar et al.
patent: 6859454 (2005-02-01), Bowes
patent: 6876952 (2005-04-01), Kappler et al.
patent: 6937601 (2005-08-01), Kim
patent: 6940861 (2005-09-01), Liu et al.
patent: 6985442 (2006-01-01), Wang et al.
patent: 7023840 (2006-04-01), Golla et al.
patent: 7039013 (2006-05-01), Ruutu et al.
patent: 7065091 (2006-06-01), Shoham et al.
patent: 7110411 (2006-09-01), Saidi et al.
patent: 7212535 (2007-05-01), Shoham et al.
patent: 7216090 (2007-05-01), LaCroix
patent: 7236491 (2007-06-01), Tsao et al.
patent: 7324536 (2008-01-01), Holtey et al.
patent: 7328231 (2008-02-01), LaCroix et al.
patent: 7349405 (2008-03-01), Deforche
patent: 7350208 (2008-03-01), Shoham
patent: 7362762 (2008-04-01), Williams et al.
patent: 7426215 (2008-09-01), Romano et al.
patent: 7457313 (2008-11-01), Patrick
patent: 2002/0077909 (2002-06-01), Kanojia et al.
patent: 2003/0076868 (2003-04-01), Desai et al.
patent: 2003/0123449 (2003-07-01), Kuhl et al.
patent: 2003/0179774 (2003-09-01), Saidi et al.
patent: 2003/0214964 (2003-11-01), Shoham et al.
patent: 2003/0231590 (2003-12-01), Zhao et al.
patent: 2005/0152374 (2005-07-01), Cohen et al.
patent: 2005/0220112 (2005-10-01), Williams et al.
patent: 2006/0029079 (2006-02-01), Cohen et al.
patent: 2006/0029080 (2006-02-01), Kappler et al.
patent: 2006/0114912 (2006-06-01), Kwan et al.
“Modular QoS CLI (MQC) Three-Level Hierarchical Policer”, Cisco Systems, Inc., San Jose, CA, Oct. 1, 2004.
U.S. Appl. No. 10/758,547, filed Jan. 14, 2004, Charny et al.
U.S. Appl. No. 10/422,167, filed Apr. 24, 2003, Kappler et al.
U.S. Appl. No. 11/022,246, filed Dec. 23, 2004, Cohen et al.
U.S. Appl. No. 11/070,932, filed Mar. 3, 2005, Kappler et al.
U.S. Appl. No. 10/913,055, filed Aug. 5, 2004, Cohen et al.
Bennett et al., “Hierarchical Packet Fair Queueing Algorithms,” IEEE/ACM Transactions on Networking (TON), vol. 5, Issue 5, Oct. 1997, pp. 675-689.
Hou et al., “Service Disciplines for Guaranteed Performance Service,” Proceedings—Fourth International Workshop on Real-Time Computing Systems and Applications, Oct. 27-29, 1997, pp. 244-250, Taipei.
Hagai et al., “Multiple Priority, Per Flow, Dual GCRA Rate Controller for ATM Switches,” Electrical and Electronic Engineers in Israel, 2000. The 21st IEEE Convention, Apr. 11-12, 2000, pp. 479-482, Tel-Aviv, Israel.
Kim et al., “Three-level Traffic Shaper and its Application to Source Clock Frequency Recovery for VBR Services in ATM Networks,” IEEE/ACM Transaction on Networking (TON), vol. 3, Issue 4, Aug. 1995, pp. 450-458.
Dixit et al., “Traffic Descriptor Mapping and Traffic Control for Frame Relay Over ATM Network,” IEEE/ACM Transactions on Networking (TON), vol. 6, Issue 1, Feb. 1998, pp. 56-70.
Bennett et al., “WF2Q: Worst-case Fair Weighted Fair Queueing,” INFOCOM '96. Fifteenth Annual Joint Conference of the IEEE Computer Societies Networking the Next Generation. Proceedings IEEE. Mar. 24-28, 1996, vol. 1, pp. 120-128.
Bennett et al., “High-Speed, Scalable, and Accurate Implementation of Fair Queueing Algorithms in ATM Networks,” ICNP '97, http://www-2.cs.cmu.edu/˜hzhang/papers/ICNP97.pdf, 1997.

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