Scheduling control system and switch

Details Scheduling control system and switch Scheduling control system and switch

2006-05-16

2006-05-16

Revak, Christopher (Department: 2131)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S412000, C370S461000, C709S213000, C709S238000

Reexamination Certificate

active

07046685

ABSTRACT:
A scheduling system is capable of causing no deterioration of characteristics even under equal and unequal loads, eliminating the necessity for high-speed repetitive scheduling and complicated arithmetic processes, simplifying its architecture and having its processing speed which does not depend upon a device capability. For attaining this system, an inter-highway pointer is updated to an adjacent line (rightward) when the scheduling for all the lines are finished. If the inter-highway pointer is updated N-times in the same direction (clockwise), the same pointer is updated to an adjacent line in a reverse direction (counterclockwise) in next N-processes of scheduling.

REFERENCES:
patent: 5509001 (1996-04-01), Tachibana et al.
patent: 5590123 (1996-12-01), Lyles et al.
patent: 5689644 (1997-11-01), Chou et al.
patent: 5926458 (1999-07-01), Yin
patent: 5956342 (1999-09-01), Manning et al.
patent: 6101193 (2000-08-01), Ohba
patent: 6262986 (2001-07-01), Oba et al.
patent: 6359861 (2002-03-01), Sui et al.
patent: 6449283 (2002-09-01), Chao et al.
patent: 6480911 (2002-11-01), Lu
patent: 6563837 (2003-05-01), Krishna et al.
patent: 6614790 (2003-09-01), Veres et al.
patent: 6654374 (2003-11-01), Fawaz et al.
patent: 6667984 (2003-12-01), Chao et al.
1998 Electronics Information and Communication Society Communication Society Conference, A study on scheduling algorithms for input buffered ATM switches, K. Kawarai, et al., Fujitsu Laboratories Ltd.
Terabit Switch Architecture using Input Queueing Technique, K. Kawarai et al., Fujitsu Laboratories Ltd.
The Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, A Study on Large Scale Input Queueing Switch Architecture, H. Tomonaga, et al., Fujitsu Laboratories, Ltd.

Affiliated with

Also associated with

Rating

Scheduling control system and switch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scheduling control system and switch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scheduling control system and switch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3610347