Optics: measuring and testing – Shape or surface configuration – Triangulation
Reexamination Certificate
2002-03-21
2004-09-14
Nguyen, Minh (Department: 2816)
Optics: measuring and testing
Shape or surface configuration
Triangulation
C356S629000, C331S044000
Reexamination Certificate
active
06791697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a scatterometry structure with an embedded ring oscillator, and various methods of using same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Given the importance of device performance, integrated circuit manufacturers expend a great deal of time and effort trying to maintain and improve device capabilities. Such efforts typically involve conducting a variety of electrical tests on the completed integrated circuit devices. Such tests may measure a variety of electrical parameters of the resulting device, e.g., operating frequency, drive current, resistivity, etc. Integrated circuit manufacturers constantly try to improve the design of the device or the manufacturing processes used to form such devices based upon an analysis of this electrical test data.
With respect to some integrated circuit products, e.g., microprocessors, a ring oscillator is typically employed to evaluate the operating speed of the integrated circuit device. An illustrative ring oscillator
10
is schematically depicted in FIG.
1
A. As shown therein, the ring oscillator
10
is typically comprised of a plurality of inverters
12
arranged in a series, with the output of an upstream inverter
12
being coupled to the input of a down-stream inverter
12
. The number of inverters
12
in a given ring oscillator
10
may vary depending upon the product being manufactured. For example, there may be
53
or
101
inverters
12
in an illustrative ring oscillator
10
.
FIG. 1B
is a more detailed schematic diagram of an illustrative inverter
12
. As shown therein, each inverter
12
is typically comprised of a P-channel transistor
14
P and an N-channel transistor
14
N. Ultimately, a variety of electrical tests may be performed on the ring oscillator
10
after its construction is complete to determine the performance characteristics of the resulting integrated circuit devices. However, such test results are not available until after the ring oscillator
10
and other integrated circuits have been substantially manufactured. That is, the electrical test data is not available for analysis and feedback as rapidly as would otherwise be desired.
Efforts have been made to measure the critical dimension of the gate electrode structures (not shown) of one or more of the transistors (P-type and/or N-type) that comprise the inverters
12
of the ring oscillator
10
in an effort to predict device performance. Typically, these critical dimension (“CD”) measurements are made using a scanning electron microscope (SEM) or other such metrology tool. However, due to continual reductions in size, the critical dimension of gate electrode structures can, in some cases, be difficult to determine through use of existing SEM metrology tools. This will become more problematic as gate electrode critical dimensions continue to decrease in the future. Moreover, given the close proximity of the millions of gate electrode structures formed above a substrate, and the inherent nature of the SEM, the data obtained by the SEM does not provide information about the entire profile of the gate electrode structure. That is, due to excessive noise and interference, the SEM can only be used to see down to about the mid-thickness level of the gate electrode. Thus, the profile of the gate electrode near the surface of the substrate may not be readily examined using existing SEM metrology tools. As a result, important information may be lost as to the critical dimension and/or profile of the gate electrode structures and the resulting impact on device performance levels.
The present invention is directed to a ring oscillator structure and various methods of using such a structure that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is generally directed to a scatterometry structure with an embedded ring oscillator, and various methods of using same. In one illustrative embodiment, the method comprises forming a ring oscillator that comprises a first grating structure comprised of a plurality of gate electrode structures for a plurality of N-channel transistors and a second grating structure comprised of a plurality of gate electrode structures for a plurality of P-channel transistors, and measuring at least one of a critical dimension and a profile of at least one of the gate electrode structures in at least one of the first grating structure and the second structure using a scatterometry tool. In a further embodiment, the method further comprises comparing the measured critical dimension and/or profile of the gate electrode structures to a model to predict at least one electrical performance characteristic of the ring oscillator, wherein the model provides a correlation between the critical dimension and/or profile of a gate electrode structure to at least one electrical performance characteristic of the ring oscillator.
In another embodiment, the method further comprises forming at least one capacitance loading structure, comprised of a plurality of features, as a portion of the ring oscillator, and measuring the critical dimension and/or profile of at least one of the features comprising the capacitance loading structure using a scatterometry tool. In further embodiments, the method further comprises comparing the measured critical dimension and/or profile of at least one of the features comprising the capacitance loading structure to a model to predict at least one electrical performance characteristic of the ring oscillator, wherein the model provides a correlation between the critical dimension and/or profile of the features comprising the capacitance loading structure to at least one electrical performance characteristic of the ring oscillator.
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Advanced Micro Devices , Inc.
Nguyen Minh
Williams Morgan & Amerson P.C.
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