Television – Image signal processing circuitry specific to television
Patent
1994-05-16
1996-04-09
Greening, Wendy R.
Television
Image signal processing circuitry specific to television
348208, 348466, 324121R, 364487, 327 9, 327 93, 327163, 327233, G01R 1334, H04N 514, H04N 5228
Patent
active
055066356
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a method for sampling an analog, periodically appearing measuring signal having phase jitter, accounting for a prior event.
In ISDN (Integrated Services Digital Network) measurement technology, measurements are made at the so-called SO interface. One of these measurements consists of analyzing certain periodic measuring signals in the form of pulses at this interface.
Measuring is intended to determine the shape of the pulses. With a pulse length of 5 .mu.s for example and a required resolution of approximately 40 ns, the pulses are scanned by a conventional sampling method.
In this method, one measured value per measured signal that appears (i.e., one measured value per pulse) is taken from the periodically appearing measuring signal (pulse). Measured value recording takes place at a first measuring point with triggering at the start of the measured signal. After each measured value is recorded, the time for the next measured value recording is delayed by a time unit that corresponds to the resolution. In this manner, the entire measured signal is gradually acquired.
This delay is accomplished in a known manner with a delay counter which, after each measured value recording, loads the number of previously recorded measuring points or evaluated measuring signals from a measured point counter as a starting value.
The constantly increasing delay is produced by counting down from the starting value. An analog-to-digital converter is triggered each time a count of zero is reached in the delay counter.
The entire measured signal is scanned and digitized by successively sampling the periodic measured signal at sequential measuring points in time.
The delay counter is controlled by a clock having a pulse rate which is determined by the resolution, for example 128 measuring points, within the measuring signal which is 5 .mu.s long (i.e., 40 ns.apprxeq.5 .mu.s/128).
The measured point counter and the delay counter are controlled by a sequencing control.
According to the provisions of the FTZ 1 TR 230/CCITT recommendation, the measured signal is to be recorded with a prior event of 2.5 .mu.s and an equally large overtravel. As a result, direct triggering in response to the measured signal to be detected is no longer possible.
The measured signal is generated digitally in a so-called ISDN terminal and is affected with a phase jitter. The amount of the phase jitter is much greater than the required measured value resolution.
The goal of the present invention is to provide a method for detecting an analog, periodically appearing measured signal having phase jitter, accounting for a prior event.
SUMMARY OF THE INVENTION
The method of the present invention achieves this goal by:
detecting the start of each measured signal by a trigger signal;
increasing the count of a measured point counter by one for each measured signal that appears;
transferring a new count on the measured point counter to a delay counter;
decrementing the count of the delay counter;
triggering a measured value recording each time the counter reads zero on the delay counter;
providing a signal to the measured point counter for a first time at a point in time which is determined by the start of a prior event in a measured signal to be recorded;
establishing a count at which the trigger signal is generated during the decrementing of the delay counter;
associating the established count on the delay counter with a respective measured value recorded; and
storing the associated established count and measured value recorded.
The invention will now be described with reference to an embodiment shown in the drawing.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a circuit for implementing the method according to the present invention.
FIG. 2 is a timing diagram which illustrates the method of the present invention.
DETAILED DESCRIPTION
FIG. 1 shows the parts of the circuit and connections required for understanding the present invention.
These parts are, specifically, an inte
REFERENCES:
patent: 4555765 (1985-11-01), Crooke et al.
patent: 4694244 (1987-09-01), Whiteside et al.
Christensen Andrew B.
Greening Wendy R.
Siemens Aktiengesellschaft
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