Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-07-09
2001-10-09
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06300928
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a driving circuit for an active matrix display device, and more particularly to a scanning circuit for driving the pixel rows of a liquid crystal display device.
2. Description of the Prior Art
Generally, a conventional liquid crystal display (LCD) used for a display device of a television or a computer includes a matrix of liquid crystal cells that are arranged at the crossovers of data lines and select lines. The select lines are sequentially selected by a select line scanner to produce the horizontal lines of the display. The data lines apply the brightness (gray scale) signals to the columns of liquid crystal cells as the select lines are sequentially selected.
Preferably, the select line scanner, which selects the horizontal lines to be displayed, is fabricated directly onto the same substrate and at the same time as the liquid crystal cells. Also, since a large number of data select lines are required for a television or computer display, and the small pixel pitch limits the space available for laying out the driver circuitry, it is essential to keep the select line scanner as simple as possible.
FIG. 1
illustrates an example of a known select line scanner as described in U.S. Pat. No. 5,510,805, issued to Sywe N. Lee. This select line scanner includes 240 select line driver stages, r1 to r240, which are cascade-connected to each other and simultaneously connected to 240 row lines, ROW 1 to ROW 240, respectively.
Each select line driver stage r1 to r240 includes a transistor M
6
for connecting a row line ROW i to a power supply VCC, and two transistors M
7
and M
8
for connecting a row line ROW i to a first ground VSS. The transistor M
6
is turned off by two transistors M
3
and MS after being turned on by a transistor M
4
. The transistor M
7
is turned on when a transistor M
1
is turned on and is turned off when a transistor M
2
is turned on. Similarly, the two transistors M
3
and M
5
are turned on when the transistor M
1
is turned on and are turned off when the transistor M
2
is turned on. Further, the transistor M
8
is turned on by two transistors M
9
and M
10
and is turned off by the transistor M
1
.
Next, each select line driver stage requires voltage signals on adjacent row lines ROW i−1 and ROW i+1, seven control/clock signals S
1,0
to S
3,0
, S
1,e
to S
3,e
, and S
4
, two ground (i.e., negative(−)) voltage sources, VSS and VSS
1
, and a single supply (i.e., positive(+)) voltage source, VCC. The scanner also allows the voltage signal on the row lines ROW i to stably maintain a low logic state during an interval at which the first clock signal remains at a high logic state.
The conventional select line scanner disclosed in U.S. Pat. No. 5,510,805 has several disadvantages. One disadvantage is that the select line scanner requires numerous clock signals. Another disadvantage is that it requires many voltage signals on adjacent row lines and lengthens the rising time of the voltage signal on each row line. Further, since the select line scanner applies a high logic of voltage signal to two row lines simultaneously during a particular time interval, it may discharge a data signal charged into liquid crystal cells. Also, since each select line driver stage includes a relatively large number of transistors, the circuit configuration of the select line scanner is complicated.
A conventional shift register stage is shown in FIG.
2
. The select line driver stage shown is described in U.S. Pat. No. 5,410,583, issued to Sherman Weisbrod, et al. While this shift register stage has a simpler configuration and fewer clock signals than the select line driver stage shown in
FIG. 1
, it still has its disadvantages.
This conventional shift register stage includes a pull-up transistor M
6
for applying a high logic of voltage signal to row line ROW i, and a pull-down transistor M
7
for applying a low logic of voltage signal to row line ROW i. The pull-up transistor M
6
is turned on by a high level of the (i−1) row line signal g
i−1
charged, via a transistor M
1
, into its gate, and allows a high level of a first clock signal C
1
applied to its drain to be supplied to an (i) number row line. Then, the pull-up transistor M
6
is turned off by a ground voltage VSS supplied via a transistor M
5
, to its gate when the (i+2) row line signal g
i+2
is enabled into a high level state. At this time, the transistor M
5
is turned on by the high level of the (i+2) row line signal g
i+2
to discharge a voltage signal charged into the gate of the pull-up transistor M
6
and into the ground VSS.
In this particular shift register stage, a supply voltage VDD is commonly applied, via a transistor M
3
, to the drain of transistor M
4
, the gates of transistor M
2
, and the pull-down transistor M
7
during an interval at which the second clock signal C
2
is enabled into a high level state. At this time, the pull-down transistor M
7
is turned on by a supply voltage VDD applied, via transistor M
3
, to its gate, thereby discharging a voltage charged onto an (i) row line ROW i into ground VSS. Also, a transistor M
2
, whose gate is supplied with the supply voltage VDD by way of the transistor M
3
, is turned on, thereby discharging a voltage charged to the gate of the pull-up transistor M
6
into ground VSS.
Meanwhile, transistor M
4
is turned on when a high level of the (i−1) row line signal g
i−1
is applied to its gate, thereby discharging a voltage charged to the gates of the pull-down transistor M
7
and transistor M
2
into the ground VSS. In the shift register stage as described above, the supply voltage VDD applied to the gate of the pull-down transistor M
7
can be set to a threshold voltage V
th
sufficient to turn on the pull-down transistor M
7
.
The conventional shift register stage disclosed in U.S. Pat. No. 5,410,583 has disadvantages. In the shift register stage, since an enabled interval of the (i−1) row line signal g
i−1
overlaps with that of the second clock signal C
2
, as shown in
FIG. 3
, four transistors M
1
, M
2
, M
3
, and M
4
are turned on at the same time. Accordingly, to provide a sufficiently high voltage to the gate of the pull-up transistor M
6
, transistor M
2
must have a small channel width and transistor M
4
must have a large channel width.
Another disadvantage is that the channel width of the pull-up transistor M
6
is limited by its gate voltage in addition to a load, (i.e. an impedance of a row line). If the transistor M
3
has the same channel width as transistor M
4
, a voltage supplied to the gate of transistor M
2
becomes VDD/2 and thereby reduces the power efficiency of the shift register stage. Finally, since transistors M
3
and M
4
are turned on at the same time an unnecessary waste of power occurs.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a scanning circuit that is capable of minimizing the number of input signals as well as rapidly switching a signal applied to row lines of a liquid crystal panel.
To achieve this and other objects of the invention, a scanning circuit according to one aspect of the present invention includes a plurality of cascaded scanning stages, each scanning stage having an input terminal and an output terminal, means for generating phase delayed scanning signals, means for producing an input signal, and output circuitry comprising a push-pull amplifier including pull-up and pull-down transistors having respective conduction paths connected in series with the output terminal thereof and respective control electrodes. The push-pull amplifier has a supply terminal for applying one of the phase delayed scanning signals, input circuitry responsive to a scan pulse applied to the input terminal for generating first and second control signals which are coupled to the control electrodes of the pull-up and pull-down transistors for conditioning the push-pull amplifier to provide output scan pulses, and means f
Hjerpe Richard
LG Electronics Inc.
Morgan & Lewis & Bockius, LLP
Nguyen Frances
LandOfFree
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