Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1996-10-02
1999-04-06
Lao, Lun-Yi
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345100, 345204, G09G 500
Patent
active
058924957
ABSTRACT:
A scanning circuit is provided with a plurality of address lines and AND circuits. The address lines respectively supply bit signals constituting an address signal and inverted bit signals, and each AND circuit conducts a logical operation on a predetermined number of bit signals and inverted bit signals selected from the bit signals and inverted bit signals supplied from the address lines. The AND circuits are connected to the address lines so that only one bit is switched when the address signal carries. Furthermore, a frequency of the least significant bit of the address signal is set to 1/4 of the dot frequency, while the two bits at the high end are set to have the same frequency and a phase difference of 90.degree. each other. With the described arrangement, a phase shift is prevented from occurring to an outputted signal when the address signal carries. Furthermore, the arrangement ensures that the scanning circuit can be realized in a simple circuit arrangement and operates at low frequencies, thereby ensuring a decrease in power consumption.
REFERENCES:
patent: 3921166 (1975-11-01), Volpe
patent: 5051739 (1991-09-01), Hayashida et al.
patent: 5153568 (1992-10-01), Shaw
U.S. Application No. 08/363,217, Katoh et al., filed Dec. 23, 1994.
Katoh Ken-ichi
Kubota Yasushi
Sakai Tamotsu
Lao Lun-Yi
Sharp Kabushiki Kaisha
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