Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-04-05
2005-04-05
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S099000, C345S211000
Reexamination Certificate
active
06876352
ABSTRACT:
A scanning circuit having such a high operation margin for the phase deviation of clock signal that its operation is stable. The scanning circuit includes a bidirectional shift register having transfer gates of a transfer unit and a feedback circuit, the operation of which is control led by four phase clocks. The scanning circuit comprises a delay circuit (101) that delays control clocks (A, B) supplied to the transfer gates of the transfer unit (103) relative to control clocks (C, D) supplied to the feedback circuit (104).
REFERENCES:
patent: 4195293 (1980-03-01), Margolin
patent: 5287025 (1994-02-01), Nishimichi
patent: 6232939 (2001-05-01), Saito et al.
patent: 60-113398 (1985-06-01), None
patent: 05-35213 (1993-02-01), None
patent: 05-035213 (1993-02-01), None
patent: 07-134277 (1995-05-01), None
patent: 07-134277 (1995-05-01), None
patent: 10-74062 (1998-03-01), None
patent: 10-074062 (1998-03-01), None
patent: 10-334685 (1998-12-01), None
patent: 10-334685 (1998-12-01), None
Sato Tetsushi
Sekine Hiroyuki
LandOfFree
Scanning circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scanning circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scanning circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3366751